The largest benefit of HT 3.0 is the near-double bandwidth increase
HyperTransport 2.0 bandwidth woes got you down? Say no more, HT 3.0 is here!
The HyperTransport Consortium just announced (PDF) the 3.0 revision of the HyperTransport interconnect. HyperTransport obtained instant fame when AMD picked up the bus protocol for the Athlon 64 and Opteron series processors. The bus is one of the industry's most open and fastest available already, but 3.0 adds dozens of new features and increased bandwidth.
The most apparent change for HT 3.0 is the bump in the data rate clock. HyperTransport 2.0 had a maximum clock of 1.4GHz; HT 3.0 increases that to 2.6GHz. This brings the total bandwidth available up to 20.8GBps. Additionally, HT 3.0 adds hot-plugging so devices can be inserted and removed from the HT layer on the fly. Power management and AC interconnect mode also played a large part in the newest standard -- HT 3.0 will now transmit up to one meter at the maximum specified clock speed with no signal loss. Effectively, HyperTransport can be used to connect from one machine to another in the correct conditions. DailyTech previously spoke to PathScale, a company focused on making high-speed InfiniBand interconnects. According to PathScale, AMD's HyperTransport interconnect provides greater overall bandwidth and scalability over anything else currently available.
Mario Cavalli, General Manager for the HyperTransport Consortium claims "The added performance and new features of HyperTransport 3.0 extend the applicability of HyperTransport Technology from chip-to-chip and board-to-board, all the way to chassis-to-chassis applications."
HT 3.0 also features an "un-ganging mode". Un-ganging simply means that the HyperTransport links can dynamically reconfigure during operation. For example, a single 1x16 HT link can be reconfigured as a 2x8 virtual HT link. The obvious use for something like this is a processor that could reconfigure itself to run SMT via two logical cores, each with its own HT link. After the SMT operation, the processor could configure itself back down to a single core.
HyperTransport 3.0 was only half of the HyperTransport Consortium's announcement today. Also announced was the HyperTransport HTX interface. HTX is a low voltage differential signaling link designed specifically for chassis-to-chassis HyperTransport interfaces. Essentially, the HTX connector allows the HyperTransport protocol to work over an external interface. One practical use for this may easily become external adaptable DRCs.
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