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Hynix to create DRAM that will use a single transistor bitcell

Innovative Silicon (ISi) and Hynix Semiconductor today announced an agreement for the Korean memory maker to license Z-RAM high-density memory intellectual property for use in its DRAM chips. The deal between the two companies is worth more than $10 million, with additional royalties in production.

Z-RAM was initially developed as the world’s lowest-cost embedded memory technology for logic-based ICs such as mobile chipsets, microprocessors, networking and other consumer applications.

Z-RAM-based DRAMs will use a single transistor bitcell – rather than a combination of transistors and capacitor elements – representing the first fundamental DRAM bitcell change since the invention of the DRAM in the early 1970s.

Although AMD was the first major licensee of Z-RAM technology, Hynix is the first with plans to bring the Z-RAM technology to the DRAM market. Both Interactive Silicon and Hynix are committing considerable engineering resources to work side-by-side on the program.

“Z-RAM promises to provide an elegant approach to manufacture dense DRAMs on nanometer processes,” said Sung-Joo Hong, VP of R&D Division at Hynix.  “We see the potential to create a new platform of products based on ISi’s innovation of Z-RAM that will help us maintain and grow our leadership position in the memory market.”

Hynix experienced a considerable growth in revenue in 2006, helping it crack the list of the 10 largest chip makers in the world. Jeff Lewis, VP marketing at ISi, believes that Hynix’s strength in the memory market will help push the growth of Z-RAM technology.

“We believe that this is a major milestone for ISi and Hynix.  Z-RAM will have a profound impact on the way DRAMs are designed and manufactured,” commented Lewis. “Since the DRAM industry sold more than $33 billion worth of product in 2006, these developments will, in turn, significantly affect the electronics industry as a whole.”

ISi’s Z-RAM stands apart from today’s standard DRAM and SRAM solutions as its single transistor bitcell architecture is the world’s smallest memory cell, making it the highest density, and therefore world’s lowest-cost semiconductor memory solution.

As Z-RAM’s architecture involves a smaller bitcell, Hynix may choose to make memory products with higher densities than what is currently possible with DRAM.

Z-RAM’s one transistor memory bitcell is made possible by harnessing the Floating Body Effect (FBE) found in circuits fabricated using SOI (silicon-on-insulator) wafers.  Moreover, since Z-RAM takes advantage of a naturally-occurring SOI effect, Z-RAM does not require exotic process changes to build capacitors or other complex structures within the memory bitcell.

Innovative Silicon will help Hynix integrate Z-RAM technology into its existing production line. As with any new technology, there may be added costs or lower yield during early production, but Z-RAM should eventually lead to better yields than current DRAM technologies due to its capacitor-less design.

“Memory chips built using ISi’s Z-RAM technology will be much smaller and cheaper to manufacture,” adds Mark-Eric Jones, ISi CEO. “We are looking forward to working with Hynix on its next generation of DRAM chips, and to bringing tremendous performance and usability advantages to end-users.”



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Great!!!
By iwod on 8/13/2007 7:30:25 AM , Rating: 4
With Z-RAM technology, does it mean we could in theory see 8 - 16GB In a Single DIMM?
It Seems Samsung are concentrating on Memory Stacking.
If these 2 technology work together we could see a HUGE increase in memory density.




RE: Great!!!
By Master Kenobi (blog) on 8/13/2007 8:04:11 AM , Rating: 2
I'm not sure how Z-Ram stacks. Given its completely different architecture it may or may not stack using similiar methods.


RE: Great!!!
By JasonMick (blog) on 8/13/2007 8:31:18 AM , Rating: 2
Well that would somewhat defeat the purpose wouldn't it? I mean the main goal of this technology to make the memory manufacturing process simpler and less costly, and stacking is making the manufacturing process inherently more complex and costly.

However, with that in mind, if your priority was pure capacity, I am sure it would stack, as you can stack transistor logic chips...

You would just need a thick enough insulator/dielectric to avoid any sort of intereference with the layer below. Really, stacking might be slightly more efficient since it would seem that charge would be more distributed than in capacitor/transistor memory cells.

Also, I would assume the same obstacles such as the difficulties in creating interconnects between layers still applies. Fortunately, where in the past you had to route connections on the corners, now through silicon via technology is allowing for chips directly between chips (which makes the most sense in your head!).

For a good article on TSV adoption read:
http://www.reghardware.co.uk/2007/04/23/samsung_ad...

Now remember, as it notes in the article, you can't expect memory stacking process to become mainstream until around 2010, 3D stacking today is very costly as the process has not been widely adopted yet. However when it is, you should see anywhere from a 2x to 4x memory density increase. However, the need for memory cooling solutions will likely also increase, as power increases exponentially with frequency...so someday those water cooled DIMMs won't look so goofy!

Another good thing about stacked memory of this variety (obviously) is that it would almost certainly be realatively cheaper to capacitor/transistor stacked memory. Of course, there is a reason why stacked memory technology is still not mainstream, and that is because of its price.

Disclaimer: please note any of my "knowledge" based remarks are based on my meager memory that remains from my solid state electronics course, and that was a while ago!


RE: Great!!!
By KernD on 8/13/2007 8:43:32 AM , Rating: 2
quote:
as power increases exponentially with frequency


Isn't it linear with frequency and exponential with voltage?


RE: Great!!!
By Azured on 8/13/2007 10:05:49 AM , Rating: 2
It is, but as you need to increase voltage to increase frequency, you can effectively state that power increases exponentially with frequency. The increase in frequency simply implies an increase in voltage to keep it stable.


RE: Great!!!
By mmarq on 8/15/2007 9:52:07 PM , Rating: 3
quote:
With Z-RAM technology, does it mean we could in theory see 8 - 16GB In a Single DIMM?


Well density is not that most compelling feature for the desktop right now, because its getting affordable to have 4GB with 2 DIMMS. But here is my view:

Theoretically the best way to double the memory capacity would be to go for ZRAM, because it has half the physical size of of a dram cell... it could be very compeling for servers.

ZRAM may have a problem with density of macro working at high speeds, and price because it uses only SOI. But ZRAM has:

zram works good at 1.2v with 0.003mA. It would use much less current than dram.

It leaks very little with 0v at standby mode and operating power ~3x lower than bulk silicon DRAM. Meaning DIMMs with ~3x less power and heat.

It is able to sustain ~1.5GHz with 1MB macro density at 65nm and ~3,5 GHz with 1MB macro density at 45nm with 2 pipelined stages. Not pipelined it would have 500Mhz at 65nm and 1.166Mhz at 45nm.

Translating for a DDR3 form, it would have the equivalent frequency of DIMMs at 4,0Ghz in the 65nm SOI process and 9,3Ghz in the 45nm SOI process. So theoretically the bandwidth would be 50Gbs at 65nm and 116,6Gbs at 45nm.

The latency would be around 2-3ns, meaning perhaps a latency between 4-6x less than the average DDR3.

So comparing with bulk silicon DRAM at the DDR3 format, a same DIMM with the memory modules made of zram could have a theoretically bandwidth/speed 2,5x at 65nm and 5,8x at 45nm superior to bulk DRAM, with 4-6x less latency, consuming ~3 times less power and sizing half of a equivalent DIMM DRAM memory module at the same process size.!!!

http://www.hotchips.org/archives/hc18/2_Mon/HC18.S...

The problem would be size with sustainable operation frequency, because the comparative numbers were extrapolated from zram with a sram like interface.

The big question would be how many arrays could be connected together in a memory chip, or how big those arrays can be, without degrading performance too much.

Theoretically its fair to suppose that we could have a DDR3 format with at least 3.2Ghz at 2,2,2,1 settings, operating with 1,3v

So if anyone has more info, please enlight us.


Why only 10 million?
By Shadowmaster625 on 8/13/2007 4:17:38 PM , Rating: 2
How can that technology only be worth $10 million in a $33 Billion market?




RE: Why only 10 million?
By Chillin1248 on 8/13/2007 6:26:18 PM , Rating: 2
quote:
The deal between the two companies is worth more than $10 million, with additional royalties in production.


-------
Chillin


RE: Why only 10 million?
By namechamps on 8/14/2007 1:14:11 AM , Rating: 2
Exactly. It's like those swiffer mops. This is a $10 million dollar mop. But the really money is in the couple hundred million in swiffer pads. Except it's chips and not swiffer pads .... and there is no mop. :)


RE: Why only 10 million?
By ninjit on 8/14/2007 5:38:08 PM , Rating: 2
Worst.. Analogy.. Ever


RE: Why only 10 million?
By murphyslabrat on 8/20/2007 6:59:30 PM , Rating: 2
Lol, excellent analogy. There is immense money in royalties, as well as it is an incentive on ISi's part to provide all the support it can. Meaning this is not just a paid-and-forgotten scenario, but a paid-and-assisting one.

While this means faster to-market times(which usually means lower prices), it might also mean higher prices do to having to pay for ISi's royalties as well.


AMD Usage
By Alpha4 on 8/13/2007 7:00:53 PM , Rating: 2
Didn't AMD acquire licenses to this technology back in 2002? I vividly recall reading suggestions from industry experts that AMD hoped to develop the technology further and employ it in the form of additional L2 or even L3 cache in future chips.




RE: AMD Usage
By Nehemoth on 8/13/2007 8:00:29 PM , Rating: 2
quote:
...AMD was the first major licensee of Z-RAM technology, Hynix is the first with plans to bring the Z-RAM technology to the DRAM market.


Yes.


RE: AMD Usage
By Alpha4 on 8/13/2007 9:01:24 PM , Rating: 2
Sorry. I meant to place emphasis on the date. They licensed the tech back in 2002 but we're yet to see anything come of it.


RE: AMD Usage
By mmarq on 8/15/2007 10:51:26 PM , Rating: 2
quote:
They licensed the tech back in 2002 but we're yet to see anything come of it.


hmmm... i don't believe that ZRAM is able to replace SRAM in any L1/L2/L3 levels. They should have tested it extensively.

Nevertheless ZRAM 'seems' very god to extend the memory buffer inside CPU chips. I don't now precisely the size but i belive core 2 and barcelona have them, along with good memory pre-fetch or pre-load schemes.

Now imagine instead lets say... 32Kb memory buffer a 256K buffer occupying the same die space... or better, putting 8-16MB of buffer with a extremely aggressive pre-fetch or pre-load scheme!...

...meaning that for the CPU cores the system RAM would be entirely represented in that buffer, and L2 or L3 levels free of trashing from pre-loads!!!... latencys would go pass orbit... and DRAM speed would became more and more irrelevant, specially for chips with IMCs like k10.(5)( can't say Nehalem, unless they change to a SOI process).

8Mb ZRAM at the 45nm process would occupy roughly 20mm2 (~100mm2 for SRAM). But at 65nm process with 35-40mm2, it is already stealing too much die space and not being able to replace SRAM, it is not viable.

So size, velocity of arrays compared with SRAM, and the consequent usefulness of the technology is what has been stopping ZRAM to appear inside chips. So expect ZRAM only at a later stage on 45nm process or at the 32nm process.


ISi?
By sviola on 8/13/2007 9:27:50 AM , Rating: 3
What is the correct name of the company? Innovative Silicon or Interactive Silicon? Both appear in the text.




RE: ISi?
By sfjf11 on 8/13/2007 2:09:46 PM , Rating: 2
another marcus article? oh no!!!!!


RE: ISi?
By DigitalFreak on 8/15/2007 4:00:44 PM , Rating: 2
Is it because of a bad understanding of Engrish, or is he just lazy?


when?
By semo on 8/14/2007 7:11:07 PM , Rating: 2
so how far is this in development. didn't get an idea of a time frame in the article.




Z-ram definately has potential
By pugster on 8/16/2007 9:31:32 PM , Rating: 2
Let's hope that they are not like Rambus who is holding out hands to every memory manufacturer for money. We might be able to see things like video cards with integrated memory or processors with huge L3 cache.




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