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In a recent interview, AMD's next generation CPU architecture gets a name and a socket

Digitimes has a follow up to its interview with AMD's Henri Richard.  We covered the first interview here yesterday. Digitimes tried to squeeze a few more details out of Richard about the upcoming K8L platform architecture.  In the first interview, Richard would not comment on K8L. 

That's not to say we're going to present K8L at Computex – don't get me wrong – but I think that that would be a good time to start to disclose more about the future because one of the strong attributes of our roadmap, both in 2006 and 2007, is socket compatibility. The nice thing we're going to do is to deliver to customers. Whatever improvements K8L will provide, they will be applicable to some of the sockets we will be introducing. Therefore, there's a certain logic, to my mind, in disclosing more at that time.

In the first interview, Richard referred to the new architecture as "8KL" instead, but Digitimes reporters did not get back to us about this idiosyncrasy.  The three sockets AMD has on the roadmap are the 1207 pin LGA Socket F for servers, Socket AM2 for the desktop and Socket S1 for mobile devices.  All three are expected to have working samples on June 6th, 2006 according to AMD's most recent roadmap. 

In response to the approach AMD will take with K8L, Richard previously claimed that future AMD micro-architectures are strictly evolutionary and not revolutionary.  In yesterday's interview, he also claimed that AMD will arrive at better performance by improving clock speeds and increasing cache sizes, but that future core technologies will have increased integer and floating-point performance.  Seeing as K8L is the only technology on the AMD roadmap for the next year or so after AM2, we can only speculate as to what Richard means by that statement. 

Update 03/15/2006: Chris Hall from Digitimes has confirmed with us that the "8KL" reference was a misquote and that Richard was really referring to K8L.

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Clock and Cache
By mrdelldude on 3/14/2006 3:30:12 PM , Rating: 2
AMD will arrive at better performance by improving clock speeds and increasing cache sizes

Are they simply following Intel's path?

RE: Clock and Cache
By Spoonbender on 3/14/2006 3:44:30 PM , Rating: 5
You mean the one that has been used for the last 30 years? Ohnoes, how shameful!

It could be because it actually works. The problem is only when you rely solely on that trick, with a chip that doesn't scale well enough.

It's literally the oldest trick in the book. And the reason is that it *always* works. Dualcore chips only help if you run multithreaded apps. Onboard FPU's only work if you have lots of FP operations. Pipelining only works when you have dependencies spred out sufficiently, and out of order execution works, but at the expense of a lot of die space. (and is sorta already included). But if you raise the clock speed, you get better performance, period. (Assuming of course you don't reduce the efficiency of any other parts of the chip)

If they've got an architecture that can scale to higher clock speeds, they'd be dumb not to use it. If they've got a small core compared to Intel's, why not use that extra space for more cache?

RE: Clock and Cache
By Xenoterranos on 3/14/2006 7:02:42 PM , Rating: 2
I agree, and with the onboard memory controller, it may work better than ever (seeing as intel's answer to the on-board controller is to increase cache size). I've wondered long and hard about why AMD hasn't scaled their cpu's up faster and harder, and why they havent used all that extra die space. I guess the real reason was marketing!

They only need to be faster by enough of a margin to be better, but with k8 and Core both basically ancestors of the PIII, and Core being the *presumably* better of the two, will K8L be enough of an evolution to hold AMD in the race until their next architecture refresh (especially with Intel scaling their Core speeds to fast?)

Im ecstatic that intel is back in the game, because that means AMD needs to start thinking again, but it worries me that this could be their best response.

RE: Clock and Cache
By pnyffeler on 3/14/2006 3:49:23 PM , Rating: 2
I'm not sure I really understand this stance by AMD. If we accept for the moment that Intel's Conroe is 10-20% faster than the current AMD processors, what good is it going to be to up the speed or throw more cache at it?

It seems pretty clear that the on-die memory controller negates any significant increase in performance.

Also, wouldn't you thing AMD would be the one to realize that you can't keep pushing up the clock speeds to compensate for an inferior processor architecture? After all, Intel tried that with Net Burst/P4, and all they got was lots of heat and an uninterupted view of the leader's backside.

RE: Clock and Cache
By blckgrffn on 3/14/2006 3:56:47 PM , Rating: 2
Do you realize how much more cache conroe has than the amdx2? That is a huge deal and can probably be directly credited with 5-10% of conroes performance advantage. If AMD ups there cache and pushes ~3.4 ghz or so, then things will probably get very interesting again.

At least interesting in the respect that the market will have choices, instead of there being one clear winner like the AMD64 vs the Prescott P4.

RE: Clock and Cache
By hans007 on 3/14/2006 4:07:12 PM , Rating: 2
a lot of conroes will only have 2mb cache actually. that is the same amount as the x2.

RE: Clock and Cache
By Bonrock on 3/14/2006 5:35:31 PM , Rating: 3
Where did you get that information? I have read quotes of Intel officials stating that all Conroe processors will have 4MB of cache. I'm not sure how much cache was in the Conroe processor that was benchmarked, but I would be surprised if Intel didn't try to put its best foot forward by using a 4MB version.

Cache has a huge impact on performance, as anyone who has taken a class on computer architecture can attest. If the benchmarked Conroe did indeed have a 4MB cache, then I think it's safe to say that a large chunk of its performance improvement can be attributed to that. If AMD manages to work a larger cache into its processors, they could close the performance gap.

RE: Clock and Cache
By Doormat on 3/14/2006 5:49:40 PM , Rating: 2

There was the same info here at DT, but the search engine sucks and I cant find the specific article.

I believe these were the benchmark parameters
By DallasTexas on 3/14/06, Rating: -1
By smitty3268 on 3/14/2006 6:30:44 PM , Rating: 2
- Overclock the FX60 just before it bursts into flames (like the AMD K5 did... or does)

Well, it was an average OC on a poorly OCing chip. AMD is probably going to have to come out with a new revision before they can bump up the clock speed too much, but its not like that was the highest OC ever done.

- Use a Celeron version of Conroe clocked for the entry level

No, this was not the cheapo version of Conroe. It would be about like a 3.6GHz Prescott right now. Fast, but there are a few steps above, especially the EE chips.

- Turn off the Conroe's cache

What? You can't turn off cache - or at least not easily outside of the factory. This chip had the full 4MB L2 cache, while cheaper versions (not benchmarked yet) will only have 2MB.

By Xenoterranos on 3/14/2006 7:05:48 PM , Rating: 2
LOL, I would buy a case of chips that could attain that performance without cache!

By Missing Ghost on 3/14/2006 7:15:29 PM , Rating: 2
I have settings to disable the caches in my computer's bios settings.

By smitty3268 on 3/14/2006 7:24:47 PM , Rating: 2
Well, it certainly isn't impossible if the hardware support is there. The Pentium M will turn off portions of its cache on-the-fly to save power. But I fail to see why anyone would think that Intel would completely disable their cache on a chip they are benchmarking. And the original post made it sound like they went into Windows Control Panel and selected "Turn off cache" or something to that affect - maybe I just read it wrong.

RE: Clock and Cache
By coldpower27 on 3/14/2006 7:17:24 PM , Rating: 2
Well Conroe has 4MB of cache, but fro desktop Intel will also ship the Allendale core which has 2MB of LV2 Cache, slated for the 241 and 209US price points at launch.

RE: Clock and Cache
By DigitalFreak on 3/14/2006 4:15:26 PM , Rating: 2
Another thing is that AMD has yet to move to a .65 micron process, where Intel already has and is basing Conroe on that. .65 micron should give the Athlon64 / Opteron quite a bit more headroom.

RE: Clock and Cache
By Viditor on 3/15/2006 6:28:46 AM , Rating: 2
Another thing is that AMD has yet to move to a .65 micron process, where Intel already has and is basing Conroe on that. .65 micron should give the Athlon64 / Opteron quite a bit more headroom

AMD is producing 65nm for sale, just not at volume production level. They announced last week that 65nm volume production starts in Aug..
The word is that AMD has already sold all of it's production for Q1, Q2, and part of Q3...I expect that the equipment changeover is already beginning (at least at 1 of the 2 Fabs that will be producing 65nm).

RE: Clock and Cache
By masher2 on 3/15/2006 12:20:39 PM , Rating: 2
I didn't see this a link?

RE: Clock and Cache
By Viditor on 3/16/2006 2:43:04 AM , Rating: 2
I didn't see this a link?

I do, but you have to register. It was Hector Ruiz at the JPMorgan conference...

RE: Clock and Cache
By JackPack on 3/14/2006 5:32:31 PM , Rating: 3
Just because Conroe _may_ be heavily affected by cache does not mean the same will be true for K8. Conroe also uses a shared L2, while K8 does not.

K8 already has a low latency path to the main memory. Chances are, adding cache will not help much with performance.

RE: Clock and Cache
By blckgrffn on 3/14/2006 5:49:43 PM , Rating: 3
Not entirely true. L2 cache is much faster than main memory and if applications can use 4 megs of local cache, then so much the better.

Don't forget you have to add the latency of the level 1 cache, the level 2 cache, and the latency of main memory to get the total latency of the ram (level 3 in the hiearchy in this case). Have a larger L2 cache will keep more memory requests from having to transverse this far.

Also, the conroe in question did indeed have 4 megs of L2 cache. The latency is unknown at this time, I believe. AMD could also enhance the speed of their L2 cache by increasing the number of sets and therefore decreasing the set size. My guess is if they do go with a larger cache, however, they will keep it the same latency as the current one. Making it faster is expensive, just check out the prescott 1 meg to 2 meg cache increase to see this and why the speed is also important.

RE: Clock and Cache
By Xenoterranos on 3/14/2006 7:14:57 PM , Rating: 2
You forget that the memory crossbar (amd) allows the CPU's to communicate with eachother at cpu speeds, whereas the shared cache (intel), although addressable by both chips, is controlled by cpu instructions which are communicated over the FSB. This significantly improves intel core-to-core data transfer speeds (as the cache-stored data won't go over the FSB) but those chip-to-ship instructions are still relatively slowed.

Real-world, you see that intel is able to match AMD's performance with ever-increasing cache sizes, but that increases die size, decreasing yeild, and increasing price. I'd hoped that AMD had a magic bullet up their sleeve that would allow them to bypass this path, and they've held out quite a while. Hopefully the move to 65nm will offset any extra costs and provide overall benefit to the consumer.

RE: Clock and Cache
By coldpower27 on 3/14/2006 7:26:56 PM , Rating: 2

Well Conroe being on 65nm has a die size of ~ 145mm2 somewhere around this range, so basically about on level with the 90nm Manchester Athlon64x2 Core, also keep in mind Intel has better cache densities then AMD for the most part and hence was able to put on quite a bit of cache on their processor.

On the other hand the move to Socket AM2 processor has increased the die to 220mm2 for the 2x1MB parts the Windsor core.

Intel is selling this CPU for 316US and higher though so I think they will make quite a bit on this core, while they have a ~ 11xmm2 Allendale 2MB cache core for the 241US and 209US price points.

If AMD just shrinks the Windsor core to 65nm the die size will reduce to 132mm2, which is a tad smaller then Conroe but larger then Allendale.

RE: Clock and Cache
By Viditor on 3/15/2006 6:31:55 AM , Rating: 2
also keep in mind Intel has better cache densities then AMD for the most part and hence was able to put on quite a bit of cache on their processor

Good point, but remember that AMD licensed Z-Ram for cache at the end of last year. Z-Ram has a density which is 5 times that of their current cache, and runs at a FAR lower power level.

RE: Clock and Cache
By coldpower27 on 3/15/2006 7:28:06 AM , Rating: 2
On this you will have to accept my skepticism until AMD releases a product with vastly superior caches densities then the cache used in Windsor.

RE: Clock and Cache
By Viditor on 3/15/2006 8:31:32 AM , Rating: 2
Skepticism noted and accepted...but may I ask why?

RE: Clock and Cache
By coldpower27 on 3/15/2006 2:32:16 PM , Rating: 2
Simple AMD and Intel both talk about how great their future products and processes are. In AMD's case I heave heard something about 40% better transistor performance compared to a generic 65nm process and that Z-RAM tech about 5 times better cache desnity, without a shred of evidence to back this up jsut their word.

Conroe is a different story however, that as we know is a good product without a doubt.

As always just because they have access to this doesn't mean it will be implemented that quickly, if and when AMD improves their cache densities in an actual product and not just hype some tech that they had acquired is when I will believe they can increase their cache densities.

For the moment their cache density will remain inferior at least until they move to the 65nm process. Though cache desnity has already been improved on the Windsor core Athlon64x2.

RE: Clock and Cache
By aguilpa1 on 3/14/2006 4:27:51 PM , Rating: 2
first off until Conroe actually exists in purchasable hardware...its vaporware that can easily end up being pushed back in development.

Currently AMD is still the boss, the big dog in performance and efficiency, its what you and I can get our paws on, right now. If AMD feels nothing more than a MB or two of extra cache and 4 or 5 hundred more MHZ of speed is enough to counter anything Intel may have by the end of the year, why should they spend any more money. This may come back to bite them in the ass or not.

They are going to sit back, let the market develop and fine tune their next generation chip, the revolutionary one. I don't think AMD expected to be in this position, Intel shot themselves in the foot with that whole netburst fiasco, having to trash generations of chips just to catch up.

Is there..
By Jedix123 on 3/14/2006 3:43:52 PM , Rating: 2
going to be a follow up interview with DallasTexas?

Good one !!
By DallasTexas on 3/14/2006 5:58:23 PM , Rating: 2
ha ha... All in good fun. No follow up interview but rumour has it AMD is hoarding is buying lipstick by the truckload. A suspect a product refresh is in the works !

Just as I predicted in my interview with DailyTecj, Henri did confirm above that cranking up the clock (and power), a new model number sticker and a little lipstick and she's god to go.

I would also urge AMD to turn up the volume on Hypertransport and puruse the sympathy factor again. The big guy vs little guy is a winner for the ladies.

By tygrus on 3/14/2006 6:39:28 PM , Rating: 2
Yeah Intel is trying to dazzle OEM's and buyers to stick with us because we'll have something much better soon.
Buyers favourable to AMD may try to put off purchases until a decent AM2 combo is released (CPU & MB). This doesn't bode well for Q1 & Q2 sales of desktops. Notebooks and servers are probably less affected. Intel is basically admitting that they are behind at the moment and want users to wait or buy into the idea that Intel will be better and not jump ship. This has worked in the past with Dell and corporates trying to standardise desktop/server deployments.

6months to a year is a long time to wait for the next big thing. In the end you could wait forever and miss out on the immediate use of something better than you have now.

The 939pin Athlon64's have been around for about 3 years before AM2. I expect a AM2 MB to be well supportted into the future. Intel has had more boards in the past and planned for the future to support various RAM and FSB's, too many for my liking. If AMD get the AM2 based Athlon64's to be performing like they are really using DDR2-800 instead of like DDR2-400 then I'll be happy. Server purchase may have to wait until next year.

By bob661 on 3/15/2006 1:08:15 AM , Rating: 2
The 939pin Athlon64's have been around for about 3 years before AM2.
It's been three years already? Time flies.

By coldpower27 on 3/15/2006 7:29:47 AM , Rating: 2
Not quite Socket 939 was intorduced in Summer of 2004 from what I recall, and Socket AM2 looks to be introduced in Summer of 2006, so 2 years.

Die size
By nrb on 3/15/2006 6:20:00 AM , Rating: 2
Correct me if I'm wrong (like I need to say that!!!) but the die size for Conroe is really quite a lot smaller than the die size for the Athlon 64 at the moment, isn't it? That suggests to me that it may be quite difficult for AMD to add lots more L2 cache to the chip without putting the price up to the point where it's hard to compete.

That, presumably, will change as soon as AMD moves to a 65nm process, and especially if they manage to move from 200mm to 300mm silicon wafers as well. But the switch-over to 65nm is likely to be at least Q4/06, possibly even Q1/07. If they are to come up with something to rival Conroe at the time Conroe actually launches I don't think extra cache is an option. 3-6 months later, yes, but not at launch.

Hopefully they'll come up with something else. :-) Lack of competition is bad all round....

RE: Die size
By coldpower27 on 3/15/2006 7:36:23 AM , Rating: 2
Well the die size, of Conroe is about the same size as a Manchester Core Athlon 64x2, which is indeed quite a bit smaller then 199mm2 Toledo, not to mention the 220mm2 Windsor core.

Even if they shrink their processor to the 65nm process Windsor would still be larger then the 2MB Allendale Core Architecture processor, but it would be a tad smaller then 4MB Conroe as it should be as Windsor still has 2x1MB of cache. This is not factoring into the fact that AMD's 65nm process is more expensive due to AMD adding SiGe and already having SOI.

The 65nm Desktop Brisbane Athlon 64x2 isnt slated till H1 2007, hopefully though AMD has some 65nm products out in other market segments by then.

RE: Die size
By Viditor on 3/15/2006 8:29:37 AM , Rating: 2
the die size for Conroe is really quite a lot smaller than the die size for the Athlon 64 at the moment, isn't it?

I have yet to see a die size number from Intel on the various Conroe chips, but:
X2 @ 1MB cache 90nm = 147 mm2
X2 @ 2MB cache 90nm = 199 mm2
Pressler @ 4MB cache 65nm = 140 mm2
Pentium D @ 2MB cache 90nm = 213mm2

As a WAG, I'd bet that Conroe will be around 140 mm2 for the 4MB as well, and ~105 mm2 for the 2MB variety.

Intel currently gets better density than AMD does on their L2, but AMD signed a license in Dec for a new type of cache memory called Z-Ram, which increases density up to five times their current density. It only works on SOI chips, but one of the cool things about it is that it requires just a fraction of the power that current types of cache use.

RE: Die size
By coldpower27 on 3/15/2006 2:25:45 PM , Rating: 2
No not quite on the Die size on the Pentium D's.

Smithfield = Monolithic 206mm2 die. 2x1MB
Presler = Dual Die 2x81mm2 dice. 2x2MB

What should be noted is that:
Manchester = 147mm2 2x512kb S939
Toledo = 199mm2 2x1MB S939
Windsor = 220mm2 2x1MB SAM2

This must be a sale marketing guy
By clnee55 on 3/15/2006 7:12:31 PM , Rating: 2
The guy can't tell between K8L or 8KL. He must be a sale marketing, not a technical marketing. A quiz for you,

What is the difference between Sale Marketing and Technical Marketing?

By Clauzii on 3/15/2006 9:49:54 PM , Rating: 2
I´ll try:
In the Sales Marketing they do all kinds of shit to get money - In the Tech Marketing they get money for doing all the shit! :)

By Viditor on 3/16/2006 2:52:04 AM , Rating: 2
The guy can't tell between K8L or 8KL. He must be a sale marketing, not a technical marketing.

It's spelled sale s marketing...I wouldn't be jumping on someone else's typos if your prone to do them yourself, mate. ;)

To answer your question though, Technical marketing is like when Intel spent $.5 billion on software development for Itanium in order to convince customers to switch.
An example of Sales marketing is the "Intel Inside" campaign.

What it means . . .
By DrMrLordX on 3/14/2006 3:01:11 PM , Rating: 2
Is that either Richard or the Digitimes were so unsatisfied with buzz on their previous article that they pumped Richard for more info to try and get people psyched up about future AMD products. I don't know that it worked.

Thanks All!
By bob661 on 3/15/2006 1:08:59 AM , Rating: 2
Thanks everyone for the VERY interesting comments. Much better than the gay as hell Intel vs. AMD crap.

blah blah blah
By Zebo on 3/15/2006 3:34:24 AM , Rating: 2
Intel said: "Hey we're going to kick your ass" and the best this marketeer can come up with is "socket compatibility"... all the proof I need AMD is gunna get a whoopin is what he's not saying just a bunch of bamboozeling.

He must be the G.W. Bush of AMD
By Regs on 3/15/2006 11:25:24 PM , Rating: 2
Get my drift?

And when increasing Cache size, you have to do a lot of optimization to the core. Including a larger and more accurate branch predictor. Cache misses can cripple 4mbs when the CPU has to regain it's order of operations every other cycle.

"I modded down, down, down, and the flames went higher." -- Sven Olsen
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