Flash successor technology may be the one Intel's been cooking up under the names "Purley" and "Apache Pass"

Intel Corp. (INTC) and Micron Tech. Inc. (MU) yesterday announced a brand new kind of 128 Gigabit nonvolatile memory (NVM) which it called "XPoint".  Slicing through the PR hype, though, a simple question was left unanswered -- what memory technology is the pair using?

I. What's Xpoint?  Hint -- it's not ReRAM

Most outlets admitted that it was an unsolved mystery what was under the hood of Xpoint.  The closest we got to an answer comes from ComputerWorld who claims to have been told "it's not ReRAM, nor memristor technology (even though it sounds remarkably similar)."

(ReRAM, aka the "memristor", is championed by Hewlett-Packard Comp. (HPQ) and Silicon Valley startup Crossbar, among others.)

what is Xpoint
What is Xpoint memory -- no, really, what is it?  Well, it's not ReRAM, that's for certain.

That's a pretty big clue -- just what is needed to crack this mystery.  But before we dive into what Xpoint is, let's consider in a broader sense what it does in layman's terms and what in means for computers and mobile devices.

NVM technology is used in long term storage.  In the modern context a single technology long dominated this space -- mechanical magnetic hard disk drives (HDDs).  But HDDs are slow.  Thus over the last decade flash memory technology -- first developed in the 1980s -- has rapidly been replacing the HDDs.

Flash -- most commonly NAND-gate based cells -- is part of a broader class of storage technologies, known as "solid state" storage.  Flash-based solid state storage has some key advantages over hard drives.  It's much faster at both reads and writes.  And it uses less power.  It also has disadvantages.  Per gigabyte it's more expensive.  And its endurance and data retention tend to be far lower than HDDs (although longevity has gradually been improved).  And while 3D structures (so-called "vertical NAND" or v-NAND technologies) have improved densities, size remains another important limitation as each bit requires a tiny circuit structure.

While flash has yet to fully displace magnetic HDD storage, top players in the storage space have been hunting for an even faster displacement.  One common goal of these next-generation technologies is to develop a "unified memory".

Intel and Micron say they've cracked the unified memory puzzle with production-ready non-volatile storage tech. which they cryptically call "Xpoint".  It's currently in wafer-scale production. (pictured)

NAND flash is quite fast, particularly on a PCI express (PCIe) or similar high speed bus (non-volatile memory over PCIe in general is referred to via the acronym NVMe).  But it's still a far cry from DRAM speeds.  DRAM, dynamic random access memory, is a volatile memory technology.  That means it only holds data until you power the machine off.  Hence modern computers need two kinds of storage -- a NVM technology (e.g. a flash solid state drive (SSD)) and a volatile storage technology (DRAM).

With the latest Haswell-E/Broadwell-compatible DDR4 memory, volatile storage can reach read speeds of around 61 GBps (Gigabytes per second) (488 Gbps) and write speeds of around 46 GBps [source].  By contrast, PCIe SSDs average about 1.3 and 0.6 GBps (10.5/5 Gbps) for sequential reads/writes, respectively [example].  "Ordinary" SATA (serial-ATA) SSDs have sequential read/write speeds of around 550/500 MBps (0.55/0.50 GBps), respectively [example].  For comparison's sake, the VelociRaptor line from Western Digital Corp. (WDC) has roughly 215 and 140 MBps  for sequential reads/writes.

So even SATA SSDs are roughly twice as fast as premium HDDs.  PCIe SSDs are about five times as fast at reads and four times as fast at writes as premium HDDs.  But DDR4 is still roughly 50 times faster than a PCIe SSD.

New technologies will be needed to find a NVM technology capable of DRAM-like speeds.  Among the candidates include:
  • Resistive RAM (ReRAM/RRAM) (aka the "memristor")
  • Ferroelectric RAM (FeRAM/FRAM)
  • Magnetoresistive random-access memory (MRAM) 
  • Phase-change memory (PCM/PCMe/PRAM/PCRAM, aka Chalcogenide RAM/CRAM)
  • conductive-bridging RAM (cbRAM, aka programmable metallization cell (PMC) memory)
  • SONOS ("Silicon-Oxide-Nitride-Oxide-Silicon") memory
  • FJRAM (Floating Junction Gate Random Access Memory)
  • Conductive metal-oxide (CMOx) memory
Here's a video from Intel on Xpoint:

The video brings us to the first point, albeit a confusing bit.  Most of these in-development NVM technologies share the ability to use a common crossbar layout (also known as "x-bar" memory or "memory matrices").  Indeed, Intel has been one of the chief proponents of adhering to this interchangeable architecture that's compatible with several of the NVM storage technologies.

Here's a diagram of that idea (with the switching element labeled as the "matrix isolation device")

[Image Source: Neale]

So the crossbar nature of Xpoint (comprised of bitlines, word lines, and storage stacks consisting of a memory element + a switching element) is gives away little about what Intel is cooking up.

II. One Giant Leap for Memory Kind?

So to figure it out, we must look for clues elsewhere.  First, we note Intel's claim that it will be cheaper than flash and use less power (while being faster).  And its expected to start sampling 128 Gigabit XPoint chips shortly.  Intel's press team claims this is the first new flash technology to be commercialized since Toshiba Corp.'s (TYO:6502) release of flash NVM storage chips in 1989.

Xpoint Intel

...and in infographic form....

Intel History of memory

Side note: that's one nice infographic.  But in terms of content its claims represent a rather revisionist view.  Various NVM technologies include MRAM, RRAM, and PRAM have reached the sampling stage and in some ccases actually been sold.  Everspin and Freescale Semiconductor, Ltd. (FSL), for example, sell low density MRAM parts.  So Intel's suggestion that the market has sat idle for two-and-a-half decades is rather silly.

Indeed it is the capacity that gives us the first major clue as to the technology driving Xpoint.  Here's an analyst review of various NVM technologies and what densities had been achieved to date:


[Image Source: EETimes]

So MRAM and FRAM were still in the Megabits range as of last year.  Thus they can be ruled out with reasonable confidence.  That leaves two technologies -- PRAM and RRAM.  And reportedly Intel already said it wasn't using RRAM.  So from the density alone and Intel's comments, it appears we have our answer -- XPoint is phase change memory (PRAM).

And then there's the history.  Micron Tech. invested heavily in PRAM development.  In Jan. 2013 it wrote:

For more than 40 years, engineers and designers have been playing with electronic devices, charge storage, potential barriers, electric fields, and electrical capacitances. The 10 years Micron has spent on phase change memory was invested in learning how to work with thermal devices, phase transition, latent heat, heat diffusion, and thermal capacitances. We basically had to change our mindset—from electronic engineering to phonon engineering.

And…we made it!

That we can now produce PCM in high volumes, with industry-standard yield, high performance, and high reliability, is thanks to the huge effort and the long hours our engineers spent digging into material properties, physical mechanisms, and process details to build a solid understanding that could be translated into design and manufacturing skills.

You are perfectly right, Alan—we had to pay our own dues! But we’re proud that we reached the finish line first.

Micron has even sold PRAM commercially.  Most notably it produced 1 Gigabit modules (w/ speeds of 400 MBps) for Nokia Oyj.'s (HEX:NOK1V) Asha line of premium feature phones (a line which would later be acquired by Microsoft Corp. (MSFT)).  Of course, the only catch is that the Micron pulled its PCM lineup last year, amid struggles with profitability.  At the time Microsoft released a brief statement, commenting:

Micron's previous two generations of PCM process technologies are not available for new designs or technology evaluation, as the company is focused on developing a follow-on process to achieve lower cost per bit, lower power and higher performance.

And on its webpage, it wrote:

Micron continues innovating with PCM. After two generations of PCM process technologies, we’re developing a follow-on process to achieve lower cost per bit, lower power, and higher performance. PCM is one of several emerging memory technologies that Micron is investing in.

It appears highly likely that XPoint is that promised "follow-on [PCM] process".

III. Through the Storage Glass

Last November some savvy analysts and investors took note of this impending launch when Intel quietly announced new Skylake architecture instructions, which included support for "persistent memory", a buzz term for unified memory.  

Patents also point conclusively to phase change memory.  The Street's Chris Ciaccia guesses:

It would be astonishing if the technology isn't ringed with patents. [It's] likely that one or the other has licensed or otherwise acquired existing technology.

Well, no need for astonishment because boy has Intel (and Micron) patented their NVM technology.  Those patents are helpful because they not only further corroborate that Xpoint is indeed the second-coming of Micron PRAM, they also elaborate on the role Intel sees it play.  Basically PRAM/PCM will fall into at least three spaces:
  • Fast in-package unified memory for future exascale Xeon Phi processors
  • Persistent storage/caches for discrete GPUs and dGPUs
  • Standalone unified memory technology for PCs/mobile devices
All of these targeted uses are discussed extensively in Intel and Micron's (but espcially Intel's) elaborate patent portfolio covering all aspects of the phase change memory.  The unified memory bit is discussed via Intel's patent on "Non-volatile random access memory (nvram) as a replacement for traditional mass storage " (U.S. Patent No. 20140297938 A1), for instance.

Other patents alluded to GPUs.  And Intel's roadmap hints at a key role for this bleeding edge NVM tech.  PCM is expected to play a key supporting role to Skylake's on-die GPU (dGPU).  It's possible that Skylake may replace (or supplement?) the 128 MB Crystalwell embedded on-die DRAM module housed aside Haswell's Iris Pro dGPU.
Iris Pro graphics
Skylake's Iris graphics may get a PCM-flavored embedded memory upgrade (Haswell w/ dGPU pictured).
[Image Source: PC Gamer]

An Intel patent assigned this April ("Atomic transactions to non-volatile memory" (U.S. Patent No. 20150095600 A1)) indicates that much like the L1-3 cache instructions in NVIDIA Corp.'s (NVDA) CUDA firmware, Intel will use atomic constructs for locking.  Also similar to CUDA, Intel will split the PCM cache into virtual blocks (see: "Block-based storage device with a memory-mapped interface" (U.S. Patent No. 20150081998 A1)), perhaps individually associated with cores.

Another patent explicitly calls out GPUs -- "A method and device to augment volatile memory in a graphics subsystem with non-volatile memory" (U.S. Patent No. 20140198116 A1).  Perhaps you remember John Carmack's megatexture technology?  Well forget what you today know as a "megatexture".  Intel's patent suggests it will empower GPUs with 64 GB of PCM or more as a buffer to store massive sets of super-high resolution textures (hello, 4K gaming!).  Today's top GPU memory-wise -- the NVIDIA Titan Z -- only has 12 GB.  Most gaming GPUs are working with 4 GB of GDDR5.  Imagine what they could do with nearly an order of magnitude more video memory.


The announcement came just a month after Intel was awarded patents on a PCM-driven exascale compute cluster ("Heterogeneous memory die stacking for energy efficient computing" (US 20140310490 A1)) and on PCM-stored firmware ("Dynamic partial power down of memory-side cache in a 2-level memory hierarchy" (U.S. Patent No. 20140304475 A1)) which describes PCs with their firmware stored in PCM chips.  The latter patent also mentions the use of DDR5 for some configurations -- yup, DDR5 is coming.  The former also has a juicy tidbit, showing that one plan for Intel consists of stacking DRAM (likely DDR5), PCM, and a CPU:


The design looks a lot like Intel's Many Integrated Core (MIC) architecture line used in Xeon Phi products (Knights Corner and Knights Landing).  It's possible that the third generation Xeon Phi chips (Knights Hill) may implement the patented PCMS stack technology.

These fat chips -- each with 50-100 cores -- will talk to each other via a fiber-optic switching backplane, as pictured above.  And yes it's patented that too -- "Computer system and method for sharing computer memory" (U.S. Patent No. 20130132587 A1).  And it's patented the connections with the stack itself -- Interlayer communications for 3d integrated circuit stack (U.S. Patent No. 20130293292 A1).

Intel Knight's Hill

Intel even hold a patent on the interconnerct protocol -- "High performance interconnect coherence protocol" (U.S. Patent No. 20140115268 A1).

One small irony is for all its billing as a DRAM-killer, a key crux of Intel's patent portfolio is hardware and firmware tools to seamlessly and optimally make use of a heterogenous pool of PCM and DRAM (perhaps DDR5).  See:

In the last of those patents Intel gushes:

PCMS offers much higher performance than NAND flash and in fact begins to approach the performance points of the Dynamic Random Access Memory (DRAM) currently used as primary dynamic storage in most client computing devices. While PCMS storage may initially be more expensive per-bit than NAND storage, that relationship is forecasted to change over time until, eventually, PCMS is less expensive than NAND. 

Intel also has several patents on data processing specialized towards PCM:
"Method and system for data de-duplication" (U.S. Patent No. 20130318288 A1)
"Compression-enabled blending of data in non-volatile memory" (U.S. Patent No. 20140250257 A1)

That IP could come in handy both for advanced rendering techniques using a PCM cache.  They also could be put to use on the Xeon Phi (Knights Hill) exascale computing front in applications like genomics (which the Xpoint press release specifically name drops) and data-mining.

Intel Micron 3D Xpoint

Micron has some interesting PCM-tied IP of its own.  This filing, for instance, offers a clever port of some v-NAND concepts to the PCM space, cutting out many bitlines, to afford for higher storage densities.

But the real goldmine is found in a patent grented to Micron in May on "Accessing Memory Cells in Parallel in a Cross Point Array" (U.S. Patent No. 20150074326 A1).  Crosspoint, "Xpoint" -- get it?  And now check out the kicker.  Here's an artist's depiction of the patented hardware from Micron:

Micron patent

Now look at the images Intel and Micron have been sharing of the structure of Xpoint:



Notice the connector stack for the PCM technology is slightly taller in PCM than in RRAM, as it has more layers.  That's reflected in Intel and Micron's artist depictions of Xpoint.

So we've come this far.  We now know that Intel and Micron are almost assuredly using PRAM.  But what is PRAM actually?  Well PRAM -- as the name implies -- stores data in the form of a phase change to a tiny atomic-level structure.  Specifically, a piece of special glass known as chalcogenide glass (chalcogenide refers to elements in Group 16, such as sulfur, tellurium, and Tellurium).

Phase change memory

Here's an example of the phase change glass on atomic level. [Image Source: Columbia University]

PCM/PRAM doesn't need transistors like DRAM.  Rather, it simply activates a tiny resistor which effectively melts" the glass, turning it to or from a crystal.  


[Image Source:]

In resent years researchers both in the private sector and in the academia space have dramatically advanced the performance of the glass nanomaterial in PRAM.  Originally it took microseconds to write and nanoseconds to read PRAM.  New materials, though have PRAM performing at picosecond speeds.

IV. Xpoint -- What we Know 

Intel cites Xpoint as having "up to" 1,000 times the performance of SSDs.  Most of that comes from PRAM behaving more like DRAM and not penalizing random writes as heavily.  Also, it readily admits that the gains will be smaller when comparing to PCIe SSDs.  Still, even for PCIe SSDs' "sweet spot" -- sequential read performance -- Intel is indicating that its Xpoint should be capable of around a ten-fold speedup.

While no speed figures were announced, I'd guess that puts Xpoint at somewhere around 12 GBps.  That's about a fourth the speed of DDR4.  But it's also faster than older/slower DDR2 and DDR3 DRAM.  

DDR2 and DDR3
Xpoint may actually be faster than older DDR2 and DDR3 modules. [Image Source: LegitReviews]

If my math is correct, Intel and Micron are justified in labelling this a potential swap out replacement for DRAM.  Of course for performance sensitive applications DDR4 or DDR5 will be used.  But for many usage scenarios, it may be possible to run exclusively off PRAM.

Endurance -- already impressive by Flash standards -- has been improving as well.  Data retention times are in the hundreds of years.  And native endurance -- the number of writes before sectors start to fail -- has seen great gains.  It is now on the order of hundreds of millions of writes per sector versus tens of thousands for the best flash.  Add in the solid state wear-leveling technology lessons learned from Flash and one could safely assume that PRAM may soon be a hardier storage technology than even trusty magnetic storage.

Intel Xpoint 3D

Intel's Xpoint chip will be a 128 Gigabit (16 GB) design.

Of course Intel and Micron aren't alone in planning a PRAM party.  South Korea's Samsung Electronics Comp., Ltd. (KRX:005930) (KRX:005935) also has been testing PRAM.  Its been steadily progressing its commercial PRAM densities: Since then Samsung has fallen somewhat silent, but it's still alluding to PRAM in its analyst briefings.  Given its rapidly rising densities several years back, it wouldn't be shocking if Samsung has 64 Gigabit or 128 Gigabit prototypes of its own waiting in the wings.

V. But What if it Isn't Phase Change Memory?

It's possible that in spite the plethora of evidence, it's not phase change memory.  The Register claims:

This is, we're told, a radical resistive-RAM technology that is bit-addressable. ... That means software can access it far more easily and quickly than block-based flash. ... It will be used as a drop-in replacement for solid-state drives and NVMe (Non-Volatile Memory Express) PCIe cards.

There are no transistors involved and it is not electron-based storage. The cell material has its resistance changed [which] provides the binary value of a cell. ... Memory cells are accessed and written or read by varying the amount of voltage sent to a selector. ... An Intel spokesperson categorically denied that it was a phase-change memory process...a memristor technology [or] spin-transfer torque. 
A Micron pitch at the 2011 Flash Memory Summit [by] Greg Atwood, a senior fellow at Micron:..Cross-point can scale by adding levels. Cross-Point uses Resistive RAM (RRAM) memory cells [or] CBRAM...Conductive Bridging RAM, which is made from a thin solid state electrolyte layer sandwiched between an oxidizable anode and an inert cathode. ... Micron has a license for this technology from Arizona State University. [The] cells are read by applying a voltage across the cell and measuring the resistance.

Atwood's deck included a slide that was astonishingly prescient. ... The 3D structure is virtually identical to the one revealed by Intel and Micron. ... Our best guess is that 3D XPoint memory uses 27nm CBRAM for the memory cell and a Schottky diode for the selector.

Given that Shottky diodes represent a key part of Intel's history -- but back in the 1960s -- the claims read almost like an elaborate prank or satire.  But assuming it's serious, the claim is pretty interesting, to say the least.  CBRAM hasn't been buzzed about nearly as much as PRAM.  

From past development we've seen densities start in the Megabit range for new technologies, eventually climbing into the Gigabit range.  If Intel and Micron are truly manufacturing a wholly new kind of NVM with a 128 Gigabit (Gbit) module right out the gates -- that would be astounding.

Furthering the impossibility of such a twist, is Intel/Micron's claim that the NVM tech will be cheaper than Flash.  Even if Intel could somehow use its process mastery to secretly develop a 128 Gbit CBRAM module, it'd seem highly unlikely that it could build it cheaper than NAND.

The chips are being made at a joint Intel-Micron fab in the Utah desert.

On the flip side Intel did hire Nishant Chandra, who developed among other things a manufacturing method for  "top-down etched silicon nanopillar Schottky diodes" and "a process for bottom-up fabrication of germanium nanowire diodes during his PhD work.  But Chandra is working at a process engineer in Hillsboro, Oreg.  Intel and Micron are reportedly designing and manufacturing Xpoint at their joint facility in Utah, as noted by The BBC.  So that's one strike against that lead.

Another strike is Intel's claim that the memory will be able to achieve up to 10x the density of NAND.  That lines up well will one of the key pitch points for PRAM.  And thus far the few commercial CBRAM offerings have trailed NAND in process density (even from a third party fab perspective).  One of the only commercial backers of CBRAM -- a Californian startup named Adesto Tech. -- is "currently porting [CBRAM] to sub 55 nm to enable higher density products."

Adesto CBRAM

Consider that modern flash is being made on the 10-19 nm node.  10x denser with CBRAM?  Sounds pretty fishy given the actual physical product we've seen to date.  Also the claimed performance -- 10x the speed of Flash at writes (the worst case scenario for Flash, mind you) and 50k write cycles (pretty much the same as Flash) of Adesto's CBRAM tech make it even more unlikely that this is CBRAM.

I would tend to say Intel doesn't want to talk about its technology for now.  So ruling out the possibility that The Register goofed (and wasn't really told that) or that the Intel spokesperson was simply misinformed, it's possible they might even be deliberately smokescreening to disguise the PCM push.

One possibility is that Intel is arguing semantics.  Intel and Micron dub their phase change memory technology "phase change memory with switch", with the switch being a special one -- an Ovonic Threshold Switch (OTS).  This makes PCMS fundamentally different than PCM.

I tend to agree with Stephen Breezy's extensive analysis for Seeking Alpha in June -- an assessment that now appears eerily prescient.  As Breezy exhaustively depicts, Intel and Micron are deeply vested in PCMS -- both in terms of spending and in terms of intellectual property.

If the pair is truly making CBRAM, then yet another big question is why so many of Intel's patents specifically call out PCMS, instead of using the broader term NVM.  Occam's razor would suggest that the simplest answer is the correct one -- Intel Micron Flash Storage (IMFS) is probably building Xpoint on single-cell PCMS.

And whatever the case may be the industry appears to be favoring MRAM in the long term over either CBRAM or PCMS.

V. Purley, Skylake, and Apache Pass -- How NVM Slots Into Intel's Roadmap

Finally, regardless of what technology Intel isuing, this is almost assuredly the "Apache Pass" component of Intel's leaked Skylake-powered "Purley" server platform:

Purley Server Platform

Intel Purley

Intel Purley

(Click to Enlarge) [Image Source: Intel via ThePlatform]

Everything is bigger with Purley.  In addition to NVM, it's also going to support up to 1.5 TB of DDR4 DRAM (2 DIMMs per channel; 6 channels) with 128 GB DRAM DIMMs (which should soon be available) [source].  Apache Pass is an 800 GB module powered by more advanced NVM technology which can fill one of those channels.  That allows for a maximum of 9.6 TB of NVM unified memory if you go all in.

It's clear the answer will come shortly, though, in terms of technology.  Skylake is expect to launch in the next couple weeks.  As Intel's first new architecture on a 14 nm process, there's plenty to be excited about -- in addition to NVM.  The timing, however, suggests that NVM may indeed be inside select client-facing Core i-Series chips for PCs, repacing the old eDRAM of Crystalwell.

Intel-Micron Xpoint chips
A pair of Xpoint NVM chips are pictured.

As for standalone NVM product, Intel and Micron don't give a hard launch date, merely stating that wafers are "in production".  That indicates within the next year they'll show up in product -- be it consumer offerings or as component for next-gen GPUs and their ilk.  My bet is that when the dust settles and the smoke clears, we'll find out that it was PCMS after all that's under the hood.



As "Brian_R170" points out NVMe was somewhat confusingly interchanged with NVM in the original version of this piece.

NVM = Non-Volatile Memory  ;  NVMe = Non-Volatile Memory Express (think PCIe)

NVMe is basically non-volatile memory technologies (flash, PRAM, ReRAM, etc.) in a package compatible with the faster PCIe bus.  It's a bit confusing though as memory starts with "Me" and many other memory acronyms append the little 'e' to denote the second letter (e.g. ReRAM = Resistive RAM).  Hope that clears things up, and a thanks to the attentive reader.


THE CMOx Hypothesis:

Founded in 2002 Unity Semiconductor Corp. had been championing another NVM technology -- conductive metal oxide (CMOx).  CMOx offers 5-10x the write speeds of NAND flash and roughly 4x the density.  The company was reportedly prepping 8 GBit chips back in 2010.

Like ReRAM/RAM, CMOx is based on resistance.  But Unity Semiconductor steadfast insisted it was "not ReRAM", as what is typically known as ReRAM is filimentary.  That is to say the resistance is in a nanowire.  By contrast CMOx involved oxygen ions migrating through sort of a pillar, changing its total resistance.  So resistance was involved, but in a bulk sense, not a filimentary sense like traditional ReRAM.

Of course, ReRAM and CMOx both used the same crossbar style write lines (which as I mentioned many other memory technologies do as well -- so not much of a clue there).

CMOx in action

CMOx in action. [Image Source: Unity Semi]

The CMOx theory goes like this.  Memory veteran (and at times mass litigator) Rambus Inc. (RMBS) acquired Unity Semi in 2012 for around $35M USD [source].  Micron was sued by Rambus over various memory technologies around 2011-2012.  Micron and fellow defendants managed to invalidate some key Rambus patents, effectively winning the case.  But in the end many of the defendants -- including Micron -- settled with Rambus and agreed to pay lesser licensing fees to make Rambus go away (more or less).

That licensing in theory could entitle Micron (and by proxy Intel-Micron Flash Storage (IMFS)) to CMOx technnology.  And then there's the personal tie-in -- three of Unity Semi's founders were Micron employees.  So the companies do share a bit of history.

I'm skeptical, however, as the speeds Intel-Micron are claim (1000x flash writes) are orders of magnitude higher than what was previously said to be possible with CMOx.  I'll admit, though that the scaling factor does line up well and the technology had seen some limited commercialization.

I'd say CMOx is more likely that CBRAM, but less likely that PRAM.  My money is still on PRAM.  But if I had to have a backup bet, I'd agree with "mgsporer" that this a plausible alternative technology given the cross licensing agreement


Followup note [8/1/2015]:

Intel has been hot on the trail of PCM for some time now. Check out this slide from one of Intel Capital's 2007 CEO Summit talks highlight the technology [via BitTech]:

Intel CEO Summit 2007

Sadly the full deck does not appear to be available online, but if 3D Xpoint is PCM, let's say it's been a long time coming for Intel (and Micron, too).

Source: Intel [press release]

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