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Intel's Core architecture bullets
Intel releases details on its Core architecture

At today’s Intel Developer Forum keynote, Intel’s CTO Justin Rattner announced that the Core architecture has four issue execution with a fourteen stage pipeline. Rattner focused on five new technologies that will make Core different than previous architectures like Netburst. The wider issue execution was obviously the first and most important announcement. However, Conroe will also feature a new 128-bit SSE optimization that will allow all SSE instructions to be completed in a single cycle.

Furthermore, Rattner announced that Core architecture will have micro-ops fusion (already present on all modern Intel processors), but that the new architecture will also include macro-ops fusion. Essentially, macro-ops fusion takes multiple high level instructions, and combines them into a single instruction. For example a “compare” and “jump” instruction can be combined into a single operation.

As we already disclosed, Core will feature shared L2 cache for all of the next generation processors – including the quad core Kentsfield/Clovertown and dual core Conroe/Merom. Intel has completely redesigned the scheduler to prevent collisions with the added bonus that advanced memory management leaves the door open to advanced gating techniques; Intel’s last important point for the Core architecture.

In a nutshell, the new gating techniques will dynamically power certain portions of the CPU on and off on the fly. Intel’s Yonah already had techniques to power off portions of the cache when not in use, but the new gating techniques on Core seem to go above and beyond just powering cache.

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Conroe Release?
By sammy2066 on 3/7/2006 8:14:41 PM , Rating: 2
When is Conroe scheduled to release? I was gonna wait for AM2, but those Conroe Benchmarks blew me away!!!

RE: Conroe Release?
By Jedi2155 on 3/7/2006 11:53:11 PM , Rating: 2
3rd Quarter :).

RE: Conroe Release?
By MarkHark on 3/8/2006 10:25:16 AM , Rating: 2
me wants one too... If they can get it out at a decent price point, it's bound to be my first Intel machine in over 15 years.

Four Issue Execution
By Questar on 3/7/2006 12:51:36 PM , Rating: 2
One thing that needs mentioning - There is not a standard way to count the number of instructions issued in a cpu.

If I recall, Intel counts instructions in a way that most people wouldn't think.

Maybe one of the DT or AT guys can clarify?

RE: Four Issue Execution
By saratoga on 3/7/2006 2:52:10 PM , Rating: 2
Intel has not released any hard facts on how Conroe is organized. I think we'll have to wait for them to actually publish the info before we'll know the details.

Woodcrest only dual not quad
By trivik12 on 3/7/2006 1:10:05 PM , Rating: 2
Woodcrest is only dual-core and not quad-core as mentioned in the article. Clovertown is the 1st quad-core from Intel.

Intel is finding new ways of improving performance despite the limitations of FSB and lack of IMC.

AMD has to play catchup once NGMA releases.

By KristopherKubicki on 3/7/2006 3:47:08 PM , Rating: 2
That was supposed to read Kentsfield/Clovertown -- sorry!


By kattanna on 3/7/2006 12:31:12 PM , Rating: 2
i'd like to see intel get back into the ring, hopefully this will help them

By JackPack on 3/7/2006 1:00:56 PM , Rating: 2
Will you guys report on the Woodcrest vs. Opteron benchmarks they ran? (35% greater performance, 5% lower power).

Dell + Clovertown?

Coming Soon to a store near you....
By Dfere on 3/8/2006 10:27:14 AM , Rating: 2

First and forememost, it willl be a while before any of this comes to market, and even longer before there is a price performance benefit that most would consider.


Mark Twain once wrote "there are lies, damn lies and then statistics". I will wait until real world comparisons such as Anandtech before I begin to consider a purchase.... The fact they mirror the term Micro Ops Fusion (admittedly the last real world well known true enhancement to current architecture) makes me wonder what real world benefit is going to exist. Especially at launch.

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