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To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.



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th wonders of AMD
By sbanjac on 12/12/2006 11:19:24 PM , Rating: 3
It is a wonder how AMD manages to follow INTEL even though it has been since ever a year behind when it comes to fabrication processes. Imagine what would happen if AMD had the resources INTEL has.




RE: th wonders of AMD
By Ender17 on 12/12/2006 11:50:59 PM , Rating: 2
Intel isn't an ACRONYM


RE: th wonders of AMD
By asliarun on 12/14/2006 1:46:51 AM , Rating: 2
"Intel isn't an ACRONYM"

Yes, it is. Intel stands for "Integrated Electronics".
Having said that, i do understand what you were trying to point out to the parent poster :-)


RE: th wonders of AMD
By bighairycamel on 12/14/2006 7:15:23 AM , Rating: 2
Then it should be called IntEl gosh darn it.


RE: th wonders of AMD
By AnnihilatorX on 12/17/2006 12:58:03 PM , Rating: 2
ACRONYM isn't an acronym either
:P

The reason he used caps is exactly the same reason as you used caps in ACRONYM, to emphasize


RE: th wonders of AMD
By Viditor on 12/13/2006 12:31:25 AM , Rating: 3
quote:
It is a wonder how AMD manages to follow INTEL even though it has been since ever a year behind when it comes to fabrication processes


1. AMD's 45nm is only 6 months behind Intel
2. The AMD/IBM 45nm process looks to be significantly better than Intel's, but in any case it is VERY different.

I don't think you can actually compare the 2 companies...for instance, if AMD had Intel's resources, they might never have been this driven.


RE: th wonders of AMD
By masher2 (blog) on 12/13/2006 12:46:37 AM , Rating: 2
> "AMD's 45nm is only 6 months behind Intel..."

Bet you a cookie otherwise....that, despite what AMD says now, their first 45nm products will be 9-12 months behind Intel's.


RE: th wonders of AMD
By Viditor on 12/13/2006 12:51:09 AM , Rating: 2
quote:
Bet you a cookie otherwise

That's a bet! (I prefer Tollhouse...)

http://news.com.com/2061-10791_3-6142714.html

"One of the big questions in the chip industry today is whether Advanced Micro Devices can make the hop to 45-nanometer manufacturing in 18 months, as the company has promised. One prominent analyst says that, so far, the chances look good...
So why the optimism? AMD (and its development partner IBM) have reduced the defect density, the measure of defects per square centimeter) on its test 45-nanometer chips. "The big issue is defects, which IBM and AMD seem to have a leg up on,"


RE: th wonders of AMD
By masher2 (blog) on 12/13/2006 1:01:12 AM , Rating: 2
Well, that article openly wonders if AMD can meet 45nm in another 18 months. Intel is supposed to meet Q307, which, even if AMD makes this goal, 6-9 months behind.

And, as that article points out, it took AMD 26 months to move from the 90 to the 65 node (27, if you consider the fact that Brisbane's probably won't be available for another month yet). For half of that 26 month period, AMD was still proclaiming it was "on track", though they clearly weren't.

Finally, I have to point out the 45nm node transition is considerably more complex than was the 65. Intel demoed 45nm chips a year ago, and they're still 9-12 months out from shipping CPUs. AMD is still having trouble showing us 65nm chips, much less 45s...I find it very hard to believe they'll be shipping them in bulk in a mere 18 months.


RE: th wonders of AMD
By Khato on 12/13/2006 1:17:10 AM , Rating: 2
Ayup, Intel will be manufacturing the 45nm CPU's come Q3'07, and shipping for revenue in Q4 I believe it is. After all, have to let the conroe refresh have some time in which to have it's fun, now don't we?

I'm ever skeptical about AMD's manufacturing, though of late they seem to have gotten better. (The initial 130nm T-bred A was late and hot, though as always, hard to say how much a process and how much a design issue.)

As to the 45nm SRAM chips, Intel's was January '06, while AMD's was April '06. The more interesting point about AMD's being that the few things I've found about it seem to imply that immersion lithography wasn't used in it. Heh, and that would be the most possible stumbling block in their 45nm process I'd think.


RE: th wonders of AMD
By Viditor on 12/13/2006 1:28:27 AM , Rating: 2
quote:
The more interesting point about AMD's being that the few things I've found about it seem to imply that immersion lithography wasn't used in it

A good point, though I haven't heard one way or the other. Remember that (unlike Intel) they have kept their processing method very much under wraps...
I have been hearing that AMD was going immersion for the last 6 months now, but i haven't seen anything concrete about it.


RE: th wonders of AMD
By Khato on 12/13/2006 1:56:20 AM , Rating: 2
Mmmmm, I don't quite remember what info on P1266 has and hasn't been released yet, going from the info on Intel's process site it isn't much. In fact, there's no mention of the tricks being implemented, just some of their results, and I'd hate to ruin a surprise.

Whereas AMD's press release today states the use of ultra-low k interconnect dielectrics and immersion lithography in their 45nm process. While the ultra-low k interconnect dielectric shouldn't pose much of a problem, I do wonder at how immersion lithography will go. After all, I don't believe that there has been any mass production with immersion lithography thus far, and I'd imagine it to require a fair bit more retooling than the norm.


RE: th wonders of AMD
By Viditor on 12/13/2006 2:08:59 AM , Rating: 2
quote:
Mmmmm, I don't quite remember what info on P1266 has and hasn't been released yet, going from the info on Intel's process site it isn't much. In fact, there's no mention of the tricks being implemented, just some of their results, and I'd hate to ruin a surprise

All that I've read so far is that they will use a new high-k metal gate that they released a white paper on a little over a year ago...
http://www.intel.com/technology/silicon/si11031.ht...


RE: th wonders of AMD
By Khato on 12/13/2006 12:06:13 PM , Rating: 2
Ahhhh, so they have released that tidbit already? You had me wondering by the comment about AMD/IBM 45nm process looking better than Intel's.

Hehe, high-k gate dielectric and metal gate electrode >> decreasing wire capacitance by a small amount and possibly etching neater lines.


RE: th wonders of AMD
By Viditor on 12/13/2006 11:59:26 PM , Rating: 2
quote:
high-k gate dielectric and metal gate electrode >> decreasing wire capacitance by a small amount and possibly etching neater lines


If that were the extent of the improvements, I would agree with you...but look again at the MASSIVE increase in PMOS and NMOS.
The new DSL process increases efficiency by as much as 80% I believe.
Don't get me wrong, Intel's high-k/metal is absolutely brilliant...and it may indeed prove to be better. At this point my GUESS is that it won't be, but that is more of a WAG than anything else.
The defect decrease from immersion will certainly help AMD's yields and should keep costs down significantly.
Either way, we are going to be seeing some awesome chips coming out over the next 2 years, and at very reasonable pricing too!


RE: th wonders of AMD
By masher2 (blog) on 12/14/06, Rating: 0
RE: th wonders of AMD
By Viditor on 12/14/2006 7:52:58 AM , Rating: 2
quote:
Its not going to reduce defect rates...in fact, the resultant increase in defect rates is one of the primary factors speaking against its use

Which is why the article on reduced defects for the IBM/AMD process is so exciting!
I seem to recall that AMD wasn't expected to be successful with SOI either...in fact Intel commented that it wasn't really possible economically until at least 45nm or below.


RE: th wonders of AMD
By Khato on 12/14/2006 1:03:48 AM , Rating: 2
Hehe, I guess that the 80% pmos/24% nmos channel drive current increase compared to unstrained transistors might be a massive increase for AMD/IBM. I'm more tempted to call it playing catch up to Intel whose strained silicon tech will be on its third process node at 45nm.

Adding greater experience in strained silicon together with the high-k gate dielectric/metal gate should result in the Intel 45nm process having even greater channel drive current than the AMD/IBM. Not to mention the fact that high-k gate dielectrics say bye bye to gate leakage.

Mmm, and I wonder how the dielectric constant of the AMD/IBM 'ultra-low-k' interconnect dielectric compares to the Intel? It's hard to say since they don't often state the actual numbers, just the results of it in comparison to another previous unknown quantity, lol.

Oh, and boo hiss to reasonable pricing! Let's get those budget machines back up over $1000 with 30% of that going to the CPU manufacturers =D


RE: th wonders of AMD
By Viditor on 12/14/2006 7:49:34 AM , Rating: 2
quote:
I'm more tempted to call it playing catch up to Intel whose strained silicon tech will be on its third process node at 45nm

It may be their 3rd node, but they still haven't been able to achieve a decent DSL...
quote:
Mmm, and I wonder how the dielectric constant of the AMD/IBM 'ultra-low-k' interconnect dielectric compares to the Intel?

I believe I read that AMD's ultra-low k is at ~2.3 for the constant. I haven't seen data on Intel yet...


And yes, as an investor in both AMD and Intel, I would sure like to see an end to this price war! :)


RE: th wonders of AMD
By joset00 on 12/16/2006 8:17:48 PM , Rating: 2
quote:
In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors .


Well noted.
I guess the statement speaks for itself; it should refer to any incremental advantage over any previous straining techniques.

quote:
Not to mention the fact that high-k gate dielectrics say bye bye to gate leakage.


Not quite. Leakage can effectively be reduced... but not avoided.

quote:
Mmm, and I wonder how the dielectric constant of the AMD/IBM 'ultra-low-k' interconnect dielectric compares to the Intel?


You mentioned it... 'ultra-low-k interconnect '. And, that's what IBM/AMD are referring to when addressing the 'big' three issues concerning process improvements, not the gate oxide itself (so much for the AMD/Intel's comparison on transistor process dielectrics...)

http://www.physorg.com/news85247225.html


Cheers!


RE: th wonders of AMD
By JumpingJack on 12/16/2006 12:04:17 AM , Rating: 2
quote:
The new DSL process increases efficiency by as much as 80% I believe.


Not hardly... AMD published 4 stressors DSL (2 of them), eSiGe, and stress memorization. Cummulative they improve PMOS 63% and NMOS 32%, the combined CMOS improvement reported by AMD is 40% (factoring inverted logic comprises a mix of NMOS and PMOS) --- and this is comparing to a transistor built without the technology, not against 90 nm, that comparison would need to be made by comparing Idsat for both at equivalent gate lengths. Even at 40%, the release 65 nm is a paultry 2.6 GHz top bin split at launch, and OC is anemic at barely 2.95 GHz stock, and 3.1 GHz (xtremesys.org/forums) using a wizz bang FX-74 cooler (which you know must be fantastic).... Suggesting the move to 65 nm helped a little in power and some in size only.

In fact, the die size of a 512x2 X2 is 112 mm^2 as reported by Semiconductor Insights (registration required), so they didn't even meet the 50% scaling factor that 90 to 65 nm should have accomplished.

AMD 65 nm is looking to be a dud.


RE: th wonders of AMD
By JumpingJack on 12/16/2006 12:08:56 AM , Rating: 2
Here is the link to the data:
http://www.realworldtech.com/page.cfm?ArticleID=RW...
4 stressors, 40% improvement over transistors without the stress -- 63% for PMOS, 32% for NMOS


RE: th wonders of AMD
By Viditor on 12/13/2006 1:19:27 AM , Rating: 5
quote:
Intel is supposed to meet Q307, which, even if AMD makes this goal, 6-9 months behind

You're confusing Q3 production with Q3 delivery ...
Intel starts production in Q3 07 for a Q1 08 delivery (possibly the end of Q4 07).
AMD is scheduled for an end of Q2 08 delivery ...
quote:
For half of that 26 month period, AMD was still proclaiming it was "on track", though they clearly weren't

Of course they were and are...
Again, it's because people read what they want to believe...
AMD has always been stating a Q2/Q3 06 production for 65nm, and a Q4 06 delivery...this has happened.
quote:
Intel demoed 45nm chips a year ago

And AMD demoed them less than 3 months after Intel...


RE: th wonders of AMD
By Shintai on 12/13/06, Rating: -1
RE: th wonders of AMD
By Viditor on 12/13/2006 9:06:55 AM , Rating: 5
Ahhh...it's Shintai, King of the Intel oscillating airflow devices! :)
quote:
AMD wanted 65nm in 2005 aswell

As I'm sure that Intel wanted 22nm in 1986...what's your point?
BTW, AMD's first working 65nm chips came out at the launch of Fab 36 in October of 2005...
quote:
Only reason AMD can say 56nm for 2006 is due to a paperlaunch, else it would be 2007

I assume you mean 65nm...(USE the preview) :)
AMD 65nm has been shipping for awhile already...it says clearly in AMD's FAQ that they are OEM-only parts.
http://tinyurl.com/y65ng5
This should be obvious as the only real difference between the 90nm and 65nm part (functionally) is that the 65nm uses much less power. For desktop, this is only really important for OEM designs, so they really aren't targeted for the channel at all.
quote:
Oh, and I forgot to add. Intel ships 45nm CPUs in Q3 2007

Hmmm...not according to Intel.
http://techreport.com/etc/2006q4/fall-idf/index.x?...
From the Fall IDF in October...look at the slide and note that Penryn isn't due to ARRIVE until after 2007.

Shipping in H2 2007 can mean Dec 31 2007, and it takes a month after initial shipping for availability.


RE: th wonders of AMD
By camped69 on 12/13/2006 11:08:57 AM , Rating: 2
Regardless, the news here in Aloha is that the fab is producing 45nm as we type.


RE: th wonders of AMD
By Shintai on 12/13/06, Rating: -1
RE: th wonders of AMD
By masher2 (blog) on 12/13/2006 8:54:37 AM , Rating: 2
> "AMD has always been stating a Q2/Q3 06 production for 65nm, and a Q4 06 delivery..."

Are memories so short? Fab 36 was initially planned to be 65nm right from the start. Early 2005, AMD was claiming it would begin 65nm processing that year, and deliver early 2006. Late 2004, they were even more aggressive, with AMD's Bob Rivest claiming this was the node in which they would "close the process gap" with Intel.

> "Intel starts production in Q3 07 for a Q1 08 delivery ..."

No once again.

quote:
11/27/2006: According to the director of Intel, the company is on-track to produce Penryn in volumes and ship them to customers in the second half of 2007 .
http://www.xbitlabs.com/news/cpu/display/200611271...

Penryn is a 45nm core, I hardly need point out.


RE: th wonders of AMD
By Viditor on 12/13/2006 9:27:25 AM , Rating: 2
quote:
Fab 36 was initially planned to be 65nm right from the start

Really? I know that Fab 36 was always to become a 65nm then 32nm Fab, but I also know that it has always been planned to start at 90nm while they get 300mm up to speed...do you have a link from them that says otherwise?
quote:
Early 2005, AMD was claiming it would begin 65nm processing that year, and deliver early 2006

I believe you mis-remember...they said 65nm would begin sampling that year (which it did), and begin production in Q2 06 (which it did) for availability in Q4 06 (which it is).

"the company is on-track to produce Penryn in volumes and ship them to customers in the second half of 2007."

And you can't see how that might be slightly in the wrong context (remember that it's not a quote, it's a summation)?
Everything Intel has published says delivery in Q1 2008...
Even if they begin shipping in November of 2007 (H2 07), availability won't occur until Q1 08...
Also, it makes NO sense for them to have availability in Q3 or Q4 as they are launching their 65nm refresh in Q3, and Penryn will be replacing these...


RE: th wonders of AMD
By masher2 (blog) on 12/13/2006 9:44:05 AM , Rating: 2
> "Really?

Really. Takes about a minute to find a few dozen sources. Here's one:

quote:
AMD opened its new chip making foundry, Fab 36, in Dresden, Germany yesterday with much fanfare. The new facility is intended to be a centerpiece of the company's growth and expansion. The foundry produces 300mm wafers using 90nm technology, but will support fabrication processes as thin as 32nm. Initial plans were for Fab 36 to produce 65nm wafers upon opening, but those plans had since changed ....
http://www.betaone.net/forum/thread-18052.html

I clearly remember hundreds of news stories from 2004, claiming Fab 36 would begin production at 65nm. Plans changed after Xmas, if I remember right.

> "I believe you mis-remember...they said 65nm would begin sampling that year (which it did), and begin production in Q2 06..."

I misremember nothing. When an AMD VP stands up and says they will "close the process gap" with Intel at 65nm, its hard to forget.

BTW, AMD went through the same thing at 90nm. They originally planned volume production Q2 04, and instead they barely hit sampling by that date.

> "Everything Intel has published says delivery in Q1 2008... "

Well, you can always claim Intel was misquoted...that's a hard thing to prove or disprove now though. However, I've seen several quotes from Intel execs claiming delivery in late 2007.



RE: th wonders of AMD
By sbanjac on 12/13/2006 4:19:30 PM , Rating: 2
Lol this subject has gone to far. You just proved in your last post what i was trying to say. It is a wonder how AMD manages to keep up, it was so with 90nm, 65 nm, even 130nm, and before that 180nm.... Market capitalization all time high of intel is 200 000 000 000 of dollars, wheres AMDs had a max market capitalization of 11 500 000 000 dollars... Even now the difference is times 10, and i don't see core2duos or quads busting FX'2 times 10. It is a meare 10 % for the money you invest...


RE: th wonders of AMD
By Viditor on 12/14/2006 12:12:54 AM , Rating: 2
I think that the problem here is that you are confusing people's guesses with actual announcements...
That forum message you linked came originally from an x-bit piece by Anton Shilov (as I suspect did most of what you Googled). His original comment was:
"The new foundry by AMD processes 300mm wafers and uses 90nm process technology, not 65nm technology as AMD said earlier. The fab is expandable and will be able to produce chips using more product lines and utilizing fabrication processes as thin as 32nm"

He did not (as he usually does) link to any statement from AMD on this, and as I have gone over most of their PRs and statements, I can say that he got it slightly wrong.

quote:
When an AMD VP stands up and says they will "close the process gap" with Intel at 65nm, its hard to forget


On this you may have a point...Rivet underestimated Intel in 2004.

quote:
Well, you can always claim Intel was misquoted...that's a hard thing to prove or disprove now though. However, I've seen several quotes from Intel execs claiming delivery in late 2007

It's not a quote, it's one of their foils from the presentation at IDF in October...pretty much black and white (or blue and white in this case).

Delivery in late Dec 2007 is not inconsistent with any of what I've been saying. There is usually at least a one month lag between delivery and availability. So delivery in Dec 07 means availability in Jan 08...


RE: th wonders of AMD
By masher2 (blog) on 12/14/2006 8:19:06 AM , Rating: 1
> "Delivery in late Dec 2007 is not inconsistent "

The statement wasn't "late December 2007". It was "second half" of 07. Personally, I expect to see delivery *and* availability of Intel's 45nm chips in the Sep timeframe.

> "I think that the problem here is that you are confusing people's guesses with actual announcements"

I think the problem here is wishful thinking on your part. Here's an older story from 2003, based on on EETimes interview with an AMD VP:

quote:
AMD and IBM said the terms of their agreement would allow them to use the jointly-developed process technologies to manufacture products in their own chip fabrication facilities and in conjunction with selected manufacturing partners. The companies expect first products based on the new 65nm technologies to appear in 2005 ...


Anyone who doesn't know that AMD was planning to have 65nm chips out substantially earlier than they did, was either asleep from 2002 to 2004, or on a desert island without Internet access.


RE: th wonders of AMD
By ChipDude on 12/13/2006 11:29:15 PM , Rating: 2
What if AMD had Intel’s process? Given the raw speed up for the same node;
90nm to 90nm and 65nm to 65nm. I'd wager that AMD product on INTEL process
(Design rules aside) would be 15-20% faster clock.


Getting a little stuffy in there....
By Goty on 12/13/2006 12:19:46 AM , Rating: 2
It's going to be really interesting in a few years when we hit that 22nm mark. That's approaching the size of individual atoms. I hope there's a new technology around by that time that can be used in place of conventional transistors or we're going to hit a brick wall in terms of performance enhancements.




RE: Getting a little stuffy in there....
By Viditor on 12/13/2006 12:34:57 AM , Rating: 2
quote:
It's going to be really interesting in a few years when we hit that 22nm mark


Agreed...the rumour is that AMD's NY Fab (due in 2012) will be attempting to work with carbon nanotubes (an area that IBM currently leads the research in), or at least some form of nano-technology.


Moderated
By Shintai on 12/13/06, Rating: -1
RE: Getting a little stuffy in there....
By bobsmith1492 on 12/13/2006 7:24:10 AM , Rating: 2
Some form of nanotechnology...

Are you saying 90, 65, and 45nm processes are not "nanotechnology?" What do you think the "n" stands for?

It irks me that people think some magical "nanotechnology" will be the answer to everything. Someone did a very, very good job at marketing the term.

All one has to do is state they are researching nanotechnology and/or AI and people will just throw money at them...


By masher2 (blog) on 12/13/2006 9:08:07 AM , Rating: 2
> "Are you saying 90, 65, and 45nm processes are not "nanotechnology?"...

Well, the original definition of nanotech was manipulation of material on or about the nanometer scale (1-10nm). However, the marketing value of the buzzword took hold, people used the term loosely, and now it encompasses anything at the 100nm scale, or even larger.


RE: Getting a little stuffy in there....
By Viditor on 12/13/2006 9:40:32 AM , Rating: 2
If you're interested, there's a decent (not too technical) article here
http://www.technologyreview.com/read_article.aspx?...

"Researchers at IBM have overcome an important obstacle to building computers based on carbon nanotubes, by developing a way to selectively arrange transistors that were made using the carbon molecules. The achievement, described in the current issue of Nano Letters, could help make large-scale integrated circuits built out of carbon nanotubes possible, leading to ultrafast, low-power processors...
According to estimates, carbon nanotubes have the potential to produce transistors that run 10 times faster than even anticipated future generations of silicon-based devices, while at the same time using less power"


As to the actual size, I'm sorry I wasn't more specific (though masher is 100% correct), the reason is that nobody knows the actual size yet...


RE: Getting a little stuffy in there....
By Goty on 12/13/2006 7:24:12 PM , Rating: 2
Nanotubes might halpe in the area of speed, but the tubes themselves are quite large on the atomic scale.


By Goty on 12/13/2006 10:13:35 PM , Rating: 2
*help...

sorry, that was ugly. Might as well use the whole preview function as long as I'm being forced to anyways =P


RE: Getting a little stuffy in there....
By masher2 (blog) on 12/13/2006 12:44:21 AM , Rating: 5
> "It's going to be really interesting in a few years when we hit that 22nm mark. That's approaching the size of individual atoms..."

22nm is 220 angstroms...and atoms are in the range of 1-6A. So there's still a long ways to go before we reach that size.


RE: Getting a little stuffy in there....
By Shintai on 12/13/2006 6:35:24 AM , Rating: 1
Well yes and no, you forget you need space between atoms. Aswell as needing several atoms to build the walls.


RE: Getting a little stuffy in there....
By masher2 (blog) on 12/13/2006 9:04:13 AM , Rating: 3
> "Well yes and no, you forget you need space between atoms"

No. Atoms in a bound state typically are _smaller_ than those in a free state. Spacing of atoms in a silicon crystal is very tight, usually less than 1A. Compared to the 650A size of the current process node, we still have a long ways to go before we start building features the size of a single atom.

And yes, you need more than one atom to build transistors...but that wasn't the point the OP was making.


RE: Getting a little stuffy in there....
By wien on 12/13/2006 10:59:12 AM , Rating: 2
Just out of curiosity... At best, how many atoms are needed to make a transistor? Does anyone know? Are we talking tens, hundreds? Are we close with current tech?


By drebo on 12/13/2006 3:46:44 PM , Rating: 2
What's more important than this, though, is that once you get to a certain size, you can no longer distinguish between an open gate and a closed gate...they simply all allow current to flow. That is the true boundry for how small we can go. If I remember correctly, it's something like 12nm, but I could be wrong.


RE: Getting a little stuffy in there....
By Goty on 12/13/2006 7:22:17 PM , Rating: 2
Well, considering the fact that the electron cloud surrounding most atoms has a diameter of about 0.3nm (read 3 Angstroms), having atoms in a crystalline structure spaced at a distance of only 1 Angstrom would be a bit difficult. I was just saying that 22nm is about the same order of magnitude as the size of the atom. You're not going to achieve many more, if any, process shrinks after that.


RE: Getting a little stuffy in there....
By masher2 (blog) on 12/13/2006 11:12:20 PM , Rating: 2
> "Well, considering the fact that the electron cloud surrounding most atoms has a diameter of about 0.3nm (read 3 Angstroms), having atoms in a crystalline structure spaced at a distance of only 1 Angstrom would be a bit difficult"

Not difficult at all. As I said earlier, atomic spacing in crystalline silicon is ~1 angstrom. Here's a link since you refuse to believe:

http://www.ornl.gov/info/press_releases/get_press_...

22nm is not "the same order of magnitude as the size of the atom". Its more than 200 times larger.

> "You're not going to achieve many more, if any, process shrinks after [22nm]."

I think otherwise. There is already research proceeding on single-atom transistors, with some rather stunning advances having been made recently. That would equate to the 0.1 nm lithography node. And even that isn't a hard stop, as there's no theoretical reason to prevent switching behavior at the subatomic level.


RE: Getting a little stuffy in there....
By Goty on 12/14/2006 10:36:19 AM , Rating: 2
Nice selective quoting there. I said about the same order, not exaclty the same. Two orders of magnitude is not that much on this scale. The wave functions of these atoms easily extend out into the nm scale under the right conditions.


By masher2 (blog) on 12/14/2006 10:45:56 AM , Rating: 1
> "I said about the same order, not exaclty the same..."

About the same order means within one order of magnitude, not 2.5 orders. And your original quote was, to be precise, "that's approaching the size of individual atoms".

> "wave functions of these atoms easily extend out into the nm scale under the right conditions..."

The wave function of an atom can extend across the entire universe under the right conditions. However, the conditions which concern us here are the bound state, within a crystalline matrix. In this particular case, its less than 1/10 of a nm.




A History of Die shrink
By jonnybradley on 12/13/2006 5:02:52 AM , Rating: 2
Could anybody be so kind as to give a brife history of shrinkage over the last decade or so. It just that things seem to be getting smaller very quickly

thanks




RE: A History of Die shrink
By keitaro on 12/13/2006 8:53:59 AM , Rating: 4
Sorry if I cannot collect everything but here's a starting point since you asked...

http://en.wikipedia.org/wiki/Intel_80486

From there, search for "Pentium", and other CPU-related keywords like "Sledgehammer" or "Clawhammer", "Barton", "Thunderbird", "Thoroughbred", "Conroe", "Dothan", and so forth. I didn't go through all of the potential keywords but I'm sure looking through the information from there that you can get a good idea as to the die-shrink timeline over the past 10-15 years. Don't forget to convert your numbers since years ago we were talking in ".xxx microns", which numerous fabrication improvements lead us to using nanometer (nm) instead.


RE: A History of Die shrink
By Dfere on 12/13/2006 10:06:39 AM , Rating: 4
I am not going to give any account of shrinkage, public or private, thanks.


RE: A History of Die shrink
By Sulphademus on 12/13/2006 10:35:28 AM , Rating: 2
Back in Pentium & P2 days you were looking at 350 and 250nm. Days of most of the P4 and Athlon XP were done on the 180 scale. Later P4 and early A64 were 130. Now we are at 90 and looking to move to 65.

Remember that these are all in nm, nanometer = one billionth of a meter. Most of the P2 and earlier tech was in microns, being millionths. (nano: inverse of giga, micro: inverse of mega... so what is the inverse of tera?)


RE: A History of Die shrink
By Wonga on 12/13/2006 11:31:01 AM , Rating: 3
Pico is below nano (so I recall), if that's what you mean.


RE: A History of Die shrink
By masher2 (blog) on 12/13/2006 11:34:02 AM , Rating: 1
> "so what is the inverse of tera?..."

"pico".


RE: A History of Die shrink
By Khato on 12/13/2006 11:59:14 AM , Rating: 2
Well, you actually have to go -quite- a ways back before gate lengths were in microns, P2 era is, as you said, a quarter of a micron at 250nm.

Going down, it's milli, micro, nano, pico, femto, atto. Heh, interwire capacitances at a 240nm process tech were measured in attoferads/um, though I'd imagine that now they might be higher.


RE: A History of Die shrink
By jonnybradley on 12/14/2006 3:55:53 AM , Rating: 2
Thanks guys, good info


Man I need to pick up a book
By Regs on 12/12/2006 11:07:50 PM , Rating: 2
Because I think by not understanding what a n or p channel is just de-bunked myself as a nerd.

Anybody care to fill me (us) in?




RE: Man I need to pick up a book
By feelingshorter on 12/12/2006 11:18:40 PM , Rating: 1
I just read it and I really have no idea what they are talking about, but why worry about the detail? Just know that processors are getting faster.


RE: Man I need to pick up a book
By JumpingJack on 12/17/2006 1:52:10 AM , Rating: 2
I will add to the discussion some --- the above posts are correct in their designation. When NMOS and PMOS are manufactured into the same circuit, it is collectively called CMOS (complimentary metal oxide semiconductor). The reason is that the differential between the two makes it much easier to design inverter circuites with fewer overall transistors (i.e. flipping the logic from what I understand -- not an EE myself).

Nonetheless, from the device physics point of view, NMOS
'uses' (for lack of a better word) electrons as the majority charge carriers while PMOS has the holes (or void of e- density) as the majority carriers. People often think of holes as "postive protons" flowing, but this is not the case. Anyway, the physics of a hole traveling through the lattice is opposite (mathematically) and different than an electron in terms of lattice interactions ... ultimately this leads to slower switching PMOS transistors when compared to NMOS transistors -- i.e. NMOS transistors have shorter gate delays.

Device speed fundamentally can be observed through basic transistor parametrics, one such parametric is saturated drive current. PMOS always has lower drive current than NMOS, so technologies that can increase PMOS are always of interest --- this is why Intel implemented SiGe into their process at 90 nm and the reason AMD is trying to do so in 65 nm. SiGe provides the correct 'kind of stress' to the PMOS channel to improve the hole mobility.



RE: Man I need to pick up a book
By masher2 (blog) on 12/12/2006 11:49:46 PM , Rating: 2
In brief, they're 'negative' and 'positive' channels, the basic building blocks of semiconductors. Put two together (n-p) and you have a diode. Put three together (n-p-n or p-n-p) and you have a transistor.


RE: Man I need to pick up a book
By Ecmaster76 on 12/13/2006 12:11:43 AM , Rating: 2
I feel your pain Regs, I took a semester of study on semiconductor physics and the only thing that learned for sure is that diodes and transistors are a lot more fun when they are black boxes defined by simple high level approximations.


RE: Man I need to pick up a book
By Khato on 12/13/2006 12:42:12 AM , Rating: 3
CMOS (complementary metal oxide semiconductor) consists of both nmos and pmos transistors. The n-channel is created in an nmos transistor when a positive gate-source voltage is applied, the resultant electric field causing excess electrons to be present, vastly increasing conductivity between gate and source. Hence with an nmos transistor, you turn it on (let current flow) by applying a voltage. The pmos transistor meanwhile conducts current when there is no voltage applied to the gate. (Oh, and the p-channel is described as being an excess of 'holes' in a thin layer beneath the gate.)

Increasing the n-channel and p-channel current as described here allows for faster switching with the same device width/capacitive load. It's one of the main advantages of the strained silicon approach to my understanding. Let's just hope that the leakage current isn't increased by the same amount.


Common Sense?
By cheetah2k on 12/13/2006 2:47:13 AM , Rating: 3
I would have thought it common sense to throw Intel into the deep end, have them develop 45nm and make the mistakes, before AMD jumped in. I think its good for AMD to take a step back and focus at the job at hand - 65nm and Quad.

At least AMD can also take Intel's fab tech onboard, spend more time developing it, and make a much better product.

Some times its not the speed that counts, its the quality




RE: Common Sense?
By ThisSpaceForRent on 12/13/2006 8:02:57 AM , Rating: 3
Quantity doesn't hurt either as shown by Intel's sales figures. You have to remember the one problem with quality is you're selling to a misinformed, mostly ignorant customer base. If I slapped a 10 Ghz sticker on something I could sell a million of them on QVC, because people just don't know any better.


RE: Common Sense?
By Shintai on 12/13/2006 8:54:34 AM , Rating: 2
There is just the tiny issue with production cost. Even if AMD could avoid all Intels mistakes. But looking on 65nm AMD is doing all the mistakes Intel didn´t.

You can roughly make 2 chips for the price of 1 with 45nm vs 65nm. And sicne the 80%+ is lowbin products, you could then have a 45nm thats worse than 65nm and still make a fortune on it. Just look on AMD, 65nm cant do highend speedbins like Intels, so you get the speedbins where the volume is.


RE: Common Sense?
By Goty on 12/13/2006 7:29:46 PM , Rating: 2
Remember the first 90nm A64s? They were slower as well. AMD likes to feel things out at the lower end and mature the process befoer attacking the high-end segments.


RE: Common Sense?
By masher2 (blog) on 12/13/2006 11:18:13 PM , Rating: 2
For good and simple reasons. The high-end segment has a higher profit margin...and is therefore less affected by manufacturing costs. The low end of the market segment is where pennies count the most, and where moving to a smaller process most affects the bottom line.


nanotech
By cs302b on 12/13/2006 9:34:10 AM , Rating: 4
Wouldn't it be funny if the factories were really small as well?




RE: nanotech
By EnzoFX on 12/13/2006 10:21:50 AM , Rating: 2
hahaha, that silly comment made me laugh out loud, i pictured it in my head


RE: nanotech
By Sulphademus on 12/13/2006 10:54:33 AM , Rating: 2
I want a Wonka brand computer made by Oompaloompas.

Also, when the computer is out of date, you can eat it. I wonder what flavor the CPU will be?


RE: nanotech
By iNGEN on 12/13/2006 12:05:33 PM , Rating: 2
Blueberry, definitely blueberry.

But, we can only have one everlasting Compuwonka each.


AMD vs INTEL technology
By ChipDude on 12/13/2006 11:40:13 PM , Rating: 2
A few general comments on this annoucement and some considerable confusing among some of the posters here.

For those that somehow think AMD process is superior for leakage because of
the SOI marketing, they are wrong. Performance/leakage is a continuum of
points. If you compare INTEL vs. AMD/IBM for the same leakage INTEL is a
good 15-30% ahead. That yields either speed or power advantage at a
constant power or speed. AMD's apparent superiority has everything to do
with design tradeoff; shallower pipelining, clock gating, sleep modes.
Process sets the base technology capability. The design choices takes it to the next level. Pentium line was all about clock speed, not
performance/watt or performance/clock. Running PenitumIV on SOI or 45nm
will still have fundamental issues. There is nothing secret in design or
process here. Its all about choices made and what you are trying to
maximize; clock frequency, power, etc.

For those that are technically inclined visit IEDM and compare the AMD/IBM
vs INTEL technology drive current at same leakage, CV/I metric. INTEL
technology is the best in the industry. IN some ways that has been their
handicap. They have given their designers so much performance, capacity,
and high yield the designers were just good enough. AMD designers had to
revolutionize their approach with inferior technology. Since the INTEL
designers were just good enough they were catchable. It'll be interesting
to see with INTEL and IDC re-energized whether AMD can still compete with
their technology handicap.

For those that believe all this noise AMD is making on catching up, AMD
realizes this and has no choice but to say they will catch Intel at 45nm
node. INTEL has said it has fixed its design issue. If AMD doesn't say they will catch on the technology side their stock will be priced accordingly.
Time will tell who is walking the talk and who is all talk. I'll predict
the CEO that is behind in 2008 will get replaced or take early retirement.

In my opinion to catch at 45nm means AMD would have had to made key and critical choices last
year on technology to be ready in 2008. I highly doubt they were thinking
that last year when those decisions were required so I will expect some choices they made will not be correct or made on limited real data. Vendor data on tools and processes like immersion are highly suspect. Remember the tool vendor is trying to convince you to drop big bucks on a new tool and make money on the tool, upgrades, and service/support. If you are boring and order dry 193nm they make much less money. Of course Immersion is glamorous and exciting, makes good press, sounds exotic and the marketing monkeys lap it up.

Look at IBM, they are all about sizzle with little meat.
You only have to look at IBM's list of choices over the past few years to
see how their track record has been.

INTEL on the other hand only annouces technology that is real and in production. They did this at 130nm, 90nm, 65nm. No early noise or marketing stuff. I'll bet they made all the big decisions already at 45nm as they must stay on the two year cycle.

Someone commented that INTEL rushes technology. I find that humorous. You
don't rush a technology into 3 multi-billion fabs and ship 40-50million CPUs
within 1 year. If you don't have high yield, performance, and good
reliability you will ruin the company margins. Last I check INTEL margins
are very good even in this pricing enviroment. What is sure is if you are a
year or two late you will get upgraded steppers and later revisions of
hardware / software that help AMD and followers. If anything you'd ask why
is AMD ramp so slow with a year learning. They use all the same suppliers
as INTEL for tools. I'm sure INTEL tricks at the equipement level are all
shared and thus I'll speculuate either due to poor process choice and or bad execution, or no guts is why AMD is so slow at ramping 300mm and 65nm.

Much is being made about immersion. Is it not more signficant that INTEL
has claimed to found a trick to use tried and true dry lithography. No
messing with new stepper platform, new resists, new yield degradation modes.
Instead they probably have other tricks.

AMD/IBM annoucements are esentially incremental improvements and adoption of
INTEl inventions. I expect AMD/IBM 45nm to offer little performance for but
lots of die compaction and some capacitance reduction. If INTEL is
successful to deliver on their historical performance of 30% per generation
then AMD is in trouble.




RE: AMD vs INTEL technology
By JumpingJack on 12/15/2006 11:34:05 PM , Rating: 2
Whollly jimminy, Mary mother of God.... someone who lurks the enthusiast forum that knows the that data and makes the right conclusion!!

To see what he means, here is the summary data ---
http://www.realworldtech.com/page.cfm?ArticleID=RW...

Intel, irrefutably, has the superior process technology in the industry... node for node, Intel has always held this advantage.

Intel @130nm > AMD @130nm
Intel @90nm > AMD @90nm

And, as we are seeing...
Intel @65nm > AMD @65nm

I would not doubt the same will certainly be true for 45 nm....

Bravo!!


RE: AMD vs INTEL technology
By joset00 on 12/16/2006 8:33:33 PM , Rating: 2
(OT), not to mention that:

1. Immersion Lithography is not mature, yet (and, AMD seems to have a lot of 'immature' techniques on the way...);

2. DSL helps... in IBM/AMD's SOI process; and costs a lot & adds delay to manufacturing, also;

3. 'Porous ultra-low-k dielectric interconnects' usually have this complex drawback: poor thermal conduction. Counter measures add up to production delay & overall costs.

Well done.


Cheers!


RE: AMD vs INTEL technology
By ChipDude on 12/17/2006 1:11:44 AM , Rating: 2
LOL; Ultra low K is like building the backend system with a house of cards. If you aren't carefuly your house of cards will collapse once you put your hot chip into a package.

I can only laugh at the last time IBM made all this noise about breakthru in LowK with SILK then to see what happenend to their poor customers.

DSL is very expensive, takes probably two extra litho layers, depositions and some etch or fancy selective implants. All expensive extra steps, yield degradation, and I can't wait to see the reverse engineering pictures of it in real production. Its funny that you see it in their papers but never in their products yet.


RE: AMD vs INTEL technology
By joset00 on 12/17/2006 1:53:10 PM , Rating: 2
Yep, the [actual] trend seems to go with high-k metal dielectrics and increased gate oxide thickness (tox), for leakage 'screening'; sometimes (and, this s appears to be the case, for some), one's led to confusion, on what concerns transistor process & interconnects; actually, IBM/AMD are addressing 'porous UL-k dielectrics' in interconnects, not in the gate oxide.
SOI is a promising technique, process-wise; however, the way it's being implemented right now, in chip's substrates, is way too costly, requires Dual-Stress Liners, spacers and it doesn't solve juction leakage.
Intel's aiming at using Fully-Depleted SOI, whenever it finds necessary; the most interesting of all is that Intel's achieving extraordinary results in its process manufacturing, stiking with 'plain old technology', namely, off-the-shelf bulk silicon & dry lithography, for instance. That, in itself, is quite an achievement! And, with that, it's gone down into the 65nm [mature] node without much hassles. Compared to IBM/AMD actual 90nm, yields are far higher & reliable (RAS), even with massive amounts of L2 cache.
In my opinion (and considering data available), AMD might really bring up significant increases in drive current, especially in pMOS... compared to its previous process, not Intel's. And, that still leaves power dissipation & leakage issues out of the equation...


Cheers!


GHz war part 2
By splint on 12/13/2006 12:56:40 AM , Rating: 3
The reduction on interconnect capacitance has me most excited. This along with improved dielectrics directly relates to switching speed which greatly impacts the clock frequency bottom line. I wonder, with all vendors obviously embracing short pipeline architectures for their next generation, will we finally see AMD beat out Intel again in the GHz race like the Atholons of yore? It now seems quite possible. I'm willing to bet that if they do they will drop their CPU performance rating number in a heartbeat.




RE: GHz war part 2
By splint on 12/13/2006 1:06:26 AM , Rating: 4
Remember that one of the main goals of Intel's abysmal netburst was to supplant AMD as the GHz king after their ego was crushed when AMD reached the magical "G" first. Now, since a short pipeline is the obvious choice, fab technology plays the largest role in clock speeds for the first time ever.


RE: GHz war part 2
By Khato on 12/13/2006 8:45:00 PM , Rating: 2
The reduction of interconnect capacitance is due to the improved 'ultra-low k' interconnect dielectrics. I wouldn't say that this necessarily has a direct impact on switching speed, as any good design is going to take wire models into effect on the transistor sizing/buffering. Besides, what exactly are interconnect capacitances like on the 45nm node anyway? The only numbers I know are from the outdate 240nm, at which time it was on the order of 20-50 aF/um - tiny in comparison to gate capacitance at the time. Though with the smaller dimensions I know full well that gate capacitance will have gone down and wire capacitance up.

Hehe, don't expect the reduced capacitances/increased current drive that the announced improvements offer to mean faster transistor switching though. Rather I'd expect that they'll just size things accordingly so that everything ends up the same, just taking up less space. After all, that will also reduce their leakage current by some amount, and leakage current may well be quite a problem for them.


don't diss intel's 45nm
By Visual on 12/13/2006 6:43:51 AM , Rating: 3
stating that intel's 45nm process would be necesserily subpar compared to IBM/AMD is pretty unfounded...

while it's true intel decided to start 45nm production without immersion, it's also a fact they've received immersion tools from nikon for evaluation and aren't ignoring the option. immersion processes will start being used in 2007 by various small manufacturers, but the tech still isn't proven and developed enough for large scale application like intel needs. so if intel wants to have 45nm working this early, the "dry" proccess is their only choice.

if immersion technology proves itself later on, if it can lead to lower costs or higher yelds, it would be quite possible for intel to refit its fabs. thats one of the good things of immersion lithography - it can be applied to current tools.
until that time, intel gets the benefit to be earlier to market with 45nm products.




RE: don't diss intel's 45nm
By evildorf on 12/13/2006 4:36:37 PM , Rating: 2
Hey, I'm new to the DT forums but I'm not understanding why the OP on this comment was modded down. Intel will indeed be first to market with a 45nm process. And, since there are no products for actual comparison, assuming the technologies AMD/IBM are implementing will produce devices with superior performance is, in fact, premature.
On another topic, is there a link to a more detailed description of the immersion tech? Are they using it for a better beam spot size? And if so, why use water instead of say, an specialized oil like in immersion microscopy?


RE: don't diss intel's 45nm
By masher2 (blog) on 12/13/2006 6:53:59 PM , Rating: 4
> "I'm not understanding why the OP on this comment was modded down."

The short answer is...because some forum visitors are immature and poorly educated.

> "Are they using it for a better beam spot size? ...why use water instead of say, an specialized oil like in immersion microscopy? "

When light travels through a material, its wavelength is reduced by the refractive index of that material. This increases its resolving power, and allows you to etch smaller features without resorting to higher-frequency light.

Water is being used primarily because its refractive index is high enough to hit the 45nm node, and using a very pure, deionized water introduces less defects than would oils.
However, water immersion is insufficient for the 32nm node. For that, I think we'll either see EUV or a oil immersion variant.


***NEWSFLASH***
By Crazyeyeskillah on 12/13/2006 10:58:22 AM , Rating: 2
IBM has been producing sub 45nm chips for quite some time, they just don't release them to the general public, or make a big deal about it because they refrain from consumer level competition. I know people that work at IBM who have confirmed this for over a year, sorry intel fanboys.




RE: ***NEWSFLASH***
By Khato on 12/13/2006 11:26:16 AM , Rating: 3
Heh, there's a difference between producing small features on a test wafer in a research lab and doing it in a full scale fab on an actual chip design that's going to be shipping for revenue. If IBM could mass produce 45nm or below right now in their fabs, they would.


RE: ***NEWSFLASH***
By Cogman on 12/15/2006 12:05:09 PM , Rating: 2
But as far as I remember, intel has only done the same thing. If this is true I believe that it puts AMD/IBM on par with what Intel has boasted to produce.


no way! this is not cool!
By starshark666 on 12/15/2006 3:56:59 AM , Rating: 2
ok, here it is... iv been working on a way to make a processor that is verticaly faster then the current 3.4Gz. sorta a project from a friend of mine dared me to do. iv studyed the way that AMD and INTEL have both made their processors and yet both of them where not up to par so i tryed making something better using their philosophy. basicaly i hit the drawing board and made a new found idea that would work well with comunication speeds. well wires are nice but they are slow. using wireless is nice but causes interfearance in the board as many devices on a mother board cause air static. then i found with extreamly low frequency u can travel through air without being effected... now by using this with a custom cut rock (i wont explain it because its mine) inside of the clock you can increase the accuracy but also adjusting the messurment of the clock would cause almost a "stream" effect within the processor. this would almost make the modern today computer look like a bad joke. now the question to me is how much of what i was drawing out was taken by AMD!?!? now dont get me wrong AMD is a good company but for crying out loud i mean jeez... i get a good idea as a 1 man army, start building on it and once again get shot out of the sky because companys like AMD and intel have some petty squavel to settel! i disagree with this thats why im going to make my idea better and make it more efficient so the next time this corperate war wont step on my toes! leason is corperations are evil!




RE: no way! this is not cool!
By starshark666 on 12/15/2006 4:13:15 AM , Rating: 2
and BTW 65NM and 45NM is really not that big of a deal this is old tech stuff that finally got pushed out of the broom closet try a 10NM chip INTEL and AMD are fighting over old tech wow... anyone who thinks this is new stuff should look a bit further into the realm of hardware design. 45NM and 65 NM is a joke no matter how u look at it. still crossing the same old junky wiring accross a chip. i laugh at this... the mission is to not make smaller and smaller but to make something run faster with out jepordising the consumers computer. size of a chip and the mass of it does not matter only the rate of infomation travling accross it.

if you are to blind to see what factors im talking about please dont reply i would not like to have foolish remarks left under my post.


AMD always delivers a more mature process than Intel
By Beenthere on 12/13/06, Rating: -1
By Viditor on 12/13/2006 12:41:59 AM , Rating: 3
quote:
Intel rushes their next gen process out the door to fool the media and consumers into thinking they are ahead on technology, but really they aren't

At the moment, they are (at least in product). The point I think you were trying to make is that Intel basically shot their whole load with C2D, and that is probably true until the end of 2008 with Nehalem...

quote:
AMD's 90 nano process arrived later but was quite superior in electrical and thermals as documented


While I agree that AMD's 90nm was superior, it wasn't THAT superior...the issue for Intel wasn't the process, it was the netburst design. Intel won't have that problem with Penryn and Nehalem...
I do agree that the new 45nm process from AMD looks amazing, and we should see some dramatic headroom from it.


RE: AMD always delivers a more mature process than Intel
By Goty on 12/13/2006 7:27:17 PM , Rating: 1
The heat issues with Prescott had nothing to do with the architecture. Similarly clocked Northwood P4s ran significantly cooler than their Prescott bretheren.


By Dactyl on 12/13/2006 8:30:26 PM , Rating: 2
The heat issues with Prescott had nothing to do with the architecture.

Now, that's just a silly thing to say. Of course it was the architecture. Dropping from 130 to 90 to 65nm helped out a lot, but Core 2 Duo at 65nm is much cooler than Pentium IV or Pentium D technology at 65nm.

What's the difference between C2D and a PD if they're both at 65nm? The architecture!


By Khato on 12/13/2006 8:30:31 PM , Rating: 2
If you want to argue that the heat issues on Prescott were due to Intel's 90nm process and not the design, then feel free to explain how Dothan decreased power usage compared to Banias despite having twice the L2 cache.


RE: AMD always delivers a more mature process than Intel
By Goty on 12/13/2006 10:17:42 PM , Rating: 2
Alright, let me rephrase this. The architecture had very little to do with Prescott's heat problems. If you will both remember, the 65nm Prescotts ran relatively cool.

And as for the Dothan-Banias argument, it's called microarchitectural improvements as well as process improvements. Not to mention the whole improved halt-state.


By Khato on 12/13/2006 11:16:11 PM , Rating: 2
Note, I stated design, not architecture. Dothan was built on the exact same process as the initial Prescott, it just was designed to make use of all the 'anti-leakage' tricks available. And if I recall correctly, the later prescotts showed better power consumption once they started doing similarly.

Oh, and that leakage thing, Intel definitely learned its lesson, hehe, let's see if it decides to bite AMD sometime soon. One of my favorite quotes thus far from an AMD person on 45nm, from http://www.infoworld.com/article/06/12/13/HNamd45n...

quote:
We've been unable to scale the size as much as we used to because of leakage. We're still putting transistors closer together, but not shrinking the gates.


By Goty on 12/14/2006 10:38:53 AM , Rating: 2
>Note, I stated design, not architecture.

I was under the impression that those were synonymous (unless, of course, you mean the physical spacing of the individual processor components).

>...it just was designed to make use of all the 'anti-leakage' tricks available.

>And if I recall correctly, the later prescotts showed better power consumption once they started doing similarly.


Both statements just echo what I said.



By JumpingJack on 12/17/2006 2:00:48 AM , Rating: 2
quote:
While I agree that AMD's 90nm was superior, it wasn't THAT superior...the issue for Intel wasn't the process, it was the netburst design.


You are incorrect that AMD's 90 nm was superior, you are correct that the Netburst design was far from optimum and was the main problem.

Device performance for both clock speed and power are a convoluted function of both design (architecture) and process.

Take, for example, a 90 nm mobile part (Dothan or Banias) clocked up to 2.8 GHz (desktop speed) and compare to AMD at the same relative clocks. The Pentium-M in this case is made on the same 90 nm process that the Pentium 4 (prescott) was made, yet trades blows with AMD but at lower power.... to extrapolate one that one company has a better process over the other simply by power and computational performance is erroneous -- it cannot be done. To compare process technology directly takes data from the fundamental transistor parametrics. (See other posts below from ChipDude, he is bang on).

Data:
http://www.matbe.com/articles/lire/298/pc-desktop-...

This is one the only sites I could find that actually did an experiment to see what a Pentium-M at desktop clock speed could do.... truly odd Intel stuck with Netburst soo long.


By czarchazm on 12/13/2006 12:45:28 AM , Rating: 2
What about architechtural differences and lower clocks (read: lower current)?

Process is extremely important, though.


By czarchazm on 12/13/2006 12:46:13 AM , Rating: 2
someone beat me to it


dang yo
By ElJefe69 on 12/13/06, Rating: -1
RE: dang yo
By Russell on 12/13/2006 3:45:31 AM , Rating: 2
Err

What?


RE: dang yo
By Sulphademus on 12/13/2006 10:38:24 AM , Rating: 4
Russell, he wants a cheap machine that wont bake his room and will run all the games he wants to play at a good speed.


RE: dang yo
By iNGEN on 12/13/2006 12:03:30 PM , Rating: 3
quote:
I just want to know if it will be below 250 dollars, use less than 60 watts at max and handle me playing a hot video game. Pwn noobs = rulz

The wirehead equivalent of Ebonics or Jive.

quote:
Russell, he wants a cheap machine that wont bake his room and will run all the games he wants to play at a good speed.

Followed by the white & nerdy translation, courtesy of Sulphademus.

Anyone remember that Ebonics language lesson mp3 that floated around the 'net about ten years ago?


RE: dang yo
By WhiteBoyFunk on 12/13/2006 12:59:26 PM , Rating: 2
Was it really started ten years ago? And yes, I remember it (what I saw was actually a slideshow) well...

I'm behind a proxy on this pc and can't look it up, but wasn't it something like -

White Guy - "You are beautiful. I would like to make love to you."
Mister T - "Damn girl, you stupid fly! Let me pull up to that bumper and smack that monkey!"

Rofl, it was pretty nice.


RE: dang yo
By masher2 (blog) on 12/13/2006 1:09:31 PM , Rating: 2
Ebonics dates back at least 20 years, and "jive" is even older. I'm sure I'm not the only person here who remembers the 'Jive Translator' from the movie Airplane.


"A politician stumbles over himself... Then they pick it out. They edit it. He runs the clip, and then he makes a funny face, and the whole audience has a Pavlovian response." -- Joe Scarborough on John Stewart over Jim Cramer

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