AMD's Spring Forum just finished up and industry insiders got a chance to sit down with DailyTech and discuss the major cornerstone of the forum, K8L.  K8L is AMD's next generation processor technology, which Henri Richard first revealed to Chris Hall at Digitimes back in March.  Richard himself described K8L as evolutionary, rather than revolutionary, and it appears as though that comment was spot on the mark from the details of K8L we've seen. 

Chuck Moore, a senior AMD Fellow, gave a presentation at AMD's Spring Forum revealing some of K8L's features. Aside from being a quad-core-friendly architecture, there are three key features that will separate K8L from K8: cache, memory and HyperTransport. 

Moore revealed that K8L will be the first AMD processor to have L3 cache since the K6 CPU.  Each core has an independent L2 cache, but the entire processor shares an L3 cache pool.  There's no word yet on exactly how much cache the K8L can hold, though the K8L will be a 65nm SOI process so AMD engineers have a bit more die real estate to play around with. 

K8L will support DDR2 and DDR3 when it becomes available, although it’s still anyone's guess as to whether or not the market will actually adopt DDR3 quickly enough to warrant using DDR3 aggressively at the core launch.  Tom Trill, Samsung's Director of DRAM Marketing, was extremely hesitant to claim DDR3 would make it to the desktop without "significant" performance gains over DDR2 -- lest anyone repeat many of the mistakes made when the industry migrated from DDR1 to DDR2.

HyperTransport 3 will be a key element of K8L.  HyperTransport 3, which was just ratified a few weeks ago, increases the frequency of the current HyperTransport bus from 1.4GHz to 2.6GHz, or from 2.8GT/s to 5.2GT/s.  Current AMD Opteron processors only support HT links operating at 1GHz, though the HT 2.0 specification allows these links to run as fast as 1.4GHz.  Non-K8 quad core processors will almost certainly take advantage of this additional headroom as data across these links gets more crowded.  However, K8L processors will have the advantage of using the full 5.2GT/s per link defined in HyperTransport 3. 

K8L processors are expected to be very co-processor friendly, allowing for additional HT and HTX interconnects specifically for math or cryptography acceleration. Current Opteron 2xx and 8xx processors use three HyperTransport links per die, but AMD's documentation did not reveal how many HyperTransport links K8L would utilize.  Recently, AMD's Phil Hester claimed embedded on-chip coprocessors were part of the company's long term plan just a few months ago.  While we may not see embedded co-processors with the K8L, it does look like the architecture is gearing towards supporting co-processors in a big way.

Behind closed doors, insiders revealed to DailyTech a few tidbits of the long term quad core roadmap.  AMD will introduce no less than four quad-core families over the next two years, with the first being Deerhound.  Deerhound, we are told, will be a Socket F server processor expected to ship late next year on the K8 -- not K8L -- architecture.   Deerhound did not appear to support FB-DIMM. 

In early 2008, AMD's corporate roadmap claims a quad core desktop CPU will make an appearance, dubbed Greyhound.  Greyhound is slated to become the first quad-core AMD chip to use the HyperTransport 3 bus, and the memory controller is slated to support DDR2 and DDR3.  Unlike Deerhound, Greyhound will use the K8L architecture, and all the goodies that come with it, including the 5.2GT/s HyperTransport support.  Unless AMD's plans change drastically between now and 2008, the processors will require a new socket.

There are very few details of the other two processor families, but hopefully future forums will get a chance to touch on some of those developments as they firm up.  However, we do know that server processor cores are expected to migrate to K8L after Deerhound. 

K8L has a few other highlights, including dynamic powering of sections of the processor -- a page taken straight out of Intel's Yonah playbook.  The p-states, as far as we can tell, will be separate for each core and the memory controller.  The K8L core will also have a 32-byte prefetch (versus 16 right now), 48-bit addressing with 1GB pages and the ability to process 128-bit SSE instructions in a single cycle, another very Intel-esque feature. 

Expect to see more tidbits over the next few days as roadmaps and transcripts are still being released.