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Hardware AMD Announces SSE5 Instruction Set
Anh Tuan Huynh (Blog) - August 30, 2007 10:58 AM
Print E-mail del.icio.us 71 comment(s) - last by Oregonian2.. on Sep 7 at 7:38 PM
Coming to a processor near you in 2009

AMD today announced its new x86-instruction set to improve performance in everyday computing tasks and applications – SSE5. AMD’s new SSE5 instruction set aims to improve performance in high-performance computing, or HPC, multimedia and security applications.

The new SSE5 instructions are available to developers today, but will not make it into AMD products until next-generation Fusion architecture with Bulldozer CPU cores. AMD announced the new instructions long before it would make it into processors “to foster an industry dialogue and solicit feedback,” continuing with the company’s open collaboration philosophy.

AMD’s SSE5 includes the following new instructions:
  • 3-Operand Instructions A computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction. The ability to execute 3-Operand Instructions is currently only possible on certain RISC architectures.
  • Fused Multiply Accumulate The 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.
Intel declined to comment on AMD’s new SSE5 instructions, nor revealed if the company plans to integrate the instructions in the future.

“We have no reason to talk about 2009 plans, theirs or ours. We love what we're doing today with processors, instructions, chipsets and software tools,” Intel public relations manager Dan Snyder said. “We've already released new SSE4 instructions that we have shown to give huge benefit to video and multimedia, and is already available to ISVs with Penryn family samples.”

SSE4 extensions have already been spotted in the wild on leaked Intel Penryn processors. SSE4a, a subset of SSE4, will make an appearance on AMD's Barcelona architecture, set to debut on September 10th, 2007.  AMD has not disclosed when or if it plans to roll out the full SSE4 extension package.

Expect AMD to release processors featuring SSE5 in 2009 with Bulldozer equipped processors such as Sandtiger.

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Forked up instruction sets
By Spyvie on 8/30/2007 4:35:20 PM , Rating: 3
Hopefully AMD will employ SSE4 on it’s processors, and Intel will adopt SSE5 if it proves to be beneficial.

Otherwise, we need the equivalent of the D.O.T. to step in and ensure standards are accepted and adhered to.




RE: Forked up instruction sets
By Spyvie on 8/30/2007 4:37:03 PM , Rating: 2
Ok, I should work on my comprehension, it says right there that AMD will adopt SSE4


RE: Forked up instruction sets
By JackBeQuick on 8/30/2007 4:38:21 PM , Rating: 2
In a way you're still right. AMD's SSE4a instructions are only a subset of SSE4 (SSE4.1 as Intel calls it). I don't know what the logic to this approach is by AMD.


RE: Forked up instruction sets
By mmarq on 9/1/2007 2:53:02 AM , Rating: 2
If nothing else considered, like a sure Fusion connection, because many of those instructions bare a strong resemblance with ATI GPU ISA... Fusion AT the ISA level!...

http://arstechnica.com/news.ars/post/20070830-amd-...

... the fact that they are most of them 3operand SMID MADD instructions, would make them far far superior to the SSE4. That is, what would take 2 instructions in SSE4 to compute, will only take 1 instruction in SSE5 for a similar operation.

Liking or not, but its fact that SSE5 is far superior to SSE4, and i see no alternative to Intel but to adopt them, or came forward with something similar. The same situation when AMD introduced AMD x86_64.


RE: Forked up instruction sets
By omnicronx on 8/30/2007 4:42:11 PM , Rating: 1
Thats not what hes getting at, will Intel adopt SSE5 is what hes asking. Intel has essentially come up with every instruction set so far (SSE-SSE4) and AMD has usually been an instruction behind. Its nice too see AMD is finally stepping into the forefront. I for one am glad, It's about time someone other than Intel got to decide things.. it will be a shame if they don't adopt it and pure B.S in my mind.


RE: Forked up instruction sets
By soydios on 8/30/2007 5:00:20 PM , Rating: 4
The AnandTech article reminds us that AMD designed the x86-64 architecture that my Intel E6600 is using to run Vista 64-bit right now.


RE: Forked up instruction sets
By omnicronx on 8/30/2007 6:49:50 PM , Rating: 2
Different scenario, here intel didnt have a choice nor is it an SSE instruction set. As i said historically intel has come up with all the SSE instruction sets, so it would be interesting to see if they will implement it, or if it will be left for the server market. Remember without software to take advantage of these instructions, (if intel decides not to implement it will anyone write any software to take advantage of said instructions) they mean absolutely nothing performance wise.


RE: Forked up instruction sets
By Oregonian2 on 8/31/2007 1:41:45 PM , Rating: 2
Intel certainly did have a choice, and they originally chose another non 32-bit compatible path for 64 bit "upgrades". You're only right in that they didn't have a choice in the sense that AMD led the way and the market forced Intel to change their strategy despite their original denials that they were going to follow AMD and do what they did.

It's the very same scenario with the addition of compatible instruction extensions and whether the market forces compatibility or not. Only difference is that the 64-bit mode was a lot bigger set of added instructions than the SSEx or AMD-NOW! sets. Fundamentally the same thing.


RE: Forked up instruction sets
By sdsdv10 on 8/30/2007 11:55:08 PM , Rating: 2
quote:
Intel has essentially come up with every instruction set so far (SSE-SSE4) and AMD has usually been an instruction behind.


Didn't AMD try a similar thing with 3DNow! http://en.wikipedia.org/wiki/3DNow!

From what I understand, it simply wasn't picked up and used by software writers.


RE: Forked up instruction sets
By subhajit on 8/31/2007 4:09:04 AM , Rating: 3
"From what I understand, it simply wasn't picked up and used by software writers"

My PowerDVD seems to use 3dNow and 3dNow Pro.


By Crank the Planet on 8/31/2007 2:29:47 PM , Rating: 3
And I think the failure of software companies to adopt these intruction sets was first felt by intel- MMX anyone?

Also, has there been widespread adoption and implementation of SS3?


RE: Forked up instruction sets
By RW on 9/1/2007 5:41:18 PM , Rating: 2
It's so obvious but nobody seems to notice that Intel+NVIDIA=AMD


Any Copyrights on the SSE name?
By ltcommanderdata on 8/30/2007 5:00:47 PM , Rating: 3
I was wondering whether there are any copyrights to the SSE and MMX names that Intel owns? SSE was originally started as a polarized opposition to 3DNow!, but I think having both Intel and AMD developing something dubbed "SSE" without a unified standard will get very convoluted very quickly. Like an SSE4a that appears to be a superset of SSE4 but is actually exclusive and SSE5 being only a partial superset. I can only imagine what would happen if Intel decided to label their next instruction set "the real SSE5" or introduce a SSE6 that completely skips over AMD's SSE5.

You know, one of the things I've found interesting is how there are little things that Intel and AMD are doing can be viewed as appealing to Apple. Intel's Penryn for example has their Super Shuffle Engine which improves SSE packing, unpacking etc. which can be viewed as an attempt to meet the functionality of the Vector Permute Unit in the G4e and G5. Similarly, the move to 3-operand SSE also seems like an appeal to Altivec programmers.




RE: Any Copyrights on the SSE name?
By phattyboombatty on 8/30/2007 6:52:58 PM , Rating: 3
AFAIK Intel and AMD entered into a mutual licensing agreement that allowed AMD to use SSE instructions. AMD agreed to allow Intel to use any SSE instructions that AMD came up with and Intel agreed to allow AMD to use any SSE instructions that Intel came up with. That way, both companies could benefit from the instruction sets that either invented.


RE: Any Copyrights on the SSE name?
By mars777 on 8/31/2007 1:08:57 AM , Rating: 3
Well being a shared dual licensed technology is good.
Anyone of the two can come up with a new instruction, and the other can implement it. I don't see anything wrong in that.

What the majority of people here care is whether will this lead to a lawsuit or not.

I personally don't care as long as this is good to the industry. I wouldn't want AMD to have 3dNow 24 and some SSE-s and Intel to have SSE 25 and some 3dNow-s.

I want them to converge.

That said i think Intel will fightback in court or not implement SSE5 since they are far back with GPGPU in their cores, and even if they implemented instructions with three operands they would be slow as hell.

This is more AMD saying to Intel:

"Well, you can do a fast core with a lot of cache on industry leading nano scale, but can you integrate efficiently parallel execution of complex data on the core?"

And it is a bold stance to say something like that when they are struggling to live ;(


RE: Any Copyrights on the SSE name?
By Khato on 8/31/07, Rating: 0
RE: Any Copyrights on the SSE name?
By BVT on 8/31/2007 10:27:18 AM , Rating: 2
Surely, there was a cross licensing use of the SSE name. They get to tag their chips with SSE 1-3 now.

As far as the subset of 4 is concerned, the AMD usage of SSE3 is also a subset. AMD did not implement hyperthreading so they did not use the full SSE3.

With the elimination of the northbridge underway, there will soon be instruction sets for each bus implementation, HyperTransport & CSI.

While all this talk of instruction sets is interesting, why wont they eliminate the 16 bit and before backward compatibility in the processors? That could really open up the field for the processor and software improvements.


RE: Any Copyrights on the SSE name?
By johnsonx on 8/31/2007 11:53:48 AM , Rating: 2
quote:
why wont they eliminate the 16 bit and before backward compatibility in the processors?


They did. In 64-bit modes, the 16-bit and real mode stuff all goes away. That's the source of some of the 64-bit Windows software incompatibility headaches: there's still some legacy 16-bit stuff floating around. A common case is a older 32-bit program that would probably run ok on 64-bit Windows IF you could get it to install, but you can't because it uses an even older 16-bit installer program.

A CPU generation or two from now, I suppose it's possible we might start seeing 64-bit only x86 processors. Existing 64-bit designs are evolved from 32-bit designs, but a new 'from-the-ground-up' redesign could simply leave out all the legacy stuff. Presumably AMD eliminated legacy support from the x64 modes for precisely this reason: to open the possiblity for future processors to completely shed all legacy support.

We probably need a 64-bit only version of Windows to be released before such a processor becomes market viable though.


RE: Any Copyrights on the SSE name?
By mars777 on 8/31/2007 12:09:36 PM , Rating: 4
There is far more than just OS support.

An X86 processor REQUIRES to run in 16 bit mode.

Why?

Well, BIOS for the first one.
BIOS is a PROGRAM a CHIP. A 16 bit program on a chip(eprom) that has around 1-2 MB. Its duty is to instruct the processor how to set-up and btw an X86-64 processor cannot boot in 64bit mode. If you want to drop 16b compatibility better ask motherboard manufacturers first... then CPU manufacturers.


By johnsonx on 8/31/2007 3:31:43 PM , Rating: 1
Actually I started a follow-up post mentioning that EFI would have to be fully implemented by then as well, since BIOS as we know it requires real mode, but then decided not to bother since that would be obvious to anyone who cares. Thank you for pointing out the obvious.