backtop


Print 24 comment(s) - last by spwatkins.. on Jun 2 at 4:10 PM


Intel's Tulsa die shot
NetBurst has one last trick, the first x86 processors with shared L3 cache

Despite all the anticipation over Intel's Core architecture and the market release of Core 2 Duo, Intel's presence in the enterprise servers (four and more sockets) with NetBurst continues strong -- although AMD is making some significant headway in this space.

According to Intel's roadmaps, the first wave of Xeon MP processors based on Intel's Tulsa core will be slated for Q4'06. DailyTech has the following information on the 7100 series of Tulsa Xeon MP processors.  Tulsa is compatible with Socket 604, on Intel's Truland platform.  Intel just announced its new LGA 771 socket, and it is not uncommon for Intel to produce multiple socket variants of processors during transition years.

Intel Server Processor Roadmap
Processor
Brand
Processor
Number

Clock Speed
FSB
L3
Cache
  Release
  Date

Xeon MP  
7140M
3.4GHz / 800MHz 16MB Q4'06

Xeon MP 
7140N
3.33GHz / 667MHz 16MB Q4'06
Xeon MP 
7130M
3.2GHz / 800MHz 8MB Q4'06
Xeon MP 
7130N
3.16GHz / 667MHz 8MB Q4'06
Xeon MP 
7120M
3.0GHz / 800MHz 4MB Q4'06
Xeon MP 
7120N
3.0GHz / 667MHz 4MB Q4'06
Xeon MP 
7110M
2.6GHz / 800MHz 4MB Q4'06
Xeon MP 
7110N
2.5GHz / 667MHz 4MB Q4'06

Xeon MP 7130 and 7140 will have a 150W power envelope, while 7110 and 7120 will use a 95W envelope.

The biggest feature of Tulsa will be large L3 cache sizes which range up to 16MB. These Tulsa processors are designed to scale to four and eight socket systems, and each Tulsa CPU contains two cores with HyperThreading support.  For those keeping track at home, an eight socket Paxville system will show 32 logical CPUs.

Tulsa is the last of Intel's Netburst lineup, but Netburst does have a few tricks not found on Core yet.  For starters, the massive amounts of L3 cache found in Tulsa cores are shared between both cores. Each CPU has an independent L2 cache still.  AMD revealed earlier this year that K8L will also use the same ideology, with independent L2 and shared L3 cache. Intel has had shared L3 cache on its Itanium 2 server lineup for years, but this is the first time such a feature has appeared on x86.

This new shared cache has several advantages -- each CPU core can use the L3 cache without sending a request back to the system I/O redundantly.  In order to manage errors in the cache, Intel has technology that already exists on Itantium 2, dubbed Pellston.  Intel has incorporated this onto Tulsa but renamed the technology to CST, or Cache Safe Technology.

Intel's Woodcrest based Xeon processors expected to launch on June 26. These Woodcrest processors do not have HyperThreading, unlike Tulsa.  Dual-core Woodcrest processors have high front side bus speeds, shared L2 caches and use the Intel Core architecture.  However, Intel has no plans to replace NetBurst for Xeon servers that use more than two sockets -- at least through Q2'07. 

In 2007, Intel will introduce Clovertown, a server varient of Kentsfield, Intel's next-generation quad-core processor. Current Xeon MP processors based on Paxville will begin to be phased out by new Tulsa cores, but the change will happen throughout most of 2007.  Intel just launched its Dempsey Xeon processors with fairly lackluster response.



Comments     Threshold


This article is over a month old, voting and posting comments is disabled

So many errors
By IntelUser2000 on 5/28/2006 9:53:22 PM , Rating: 1
quote:
Xeon MP 7130 and 7140 will have a 150W power envelope, while 7110 and 7120 will use a 95W envelope.


Wrong, the ones labeled "M" is 150W, and the ones labeled "N" is 95W power envelope.

quote:
Intel has had shared L3 cache on its Itanium 2 server lineup for years, but this is the first time such a feature has appeared on x86.


Again, WRONG!!! Itanium 2 server CPUs have SEPERATE caches, not shared. Dailytech sucks.




RE: So many errors
By KristopherKubicki (blog) on 5/28/2006 10:58:50 PM , Rating: 4
I guess we are going to have to agree to disagree, but the M stands for 800MHz FSB while the N stands for 667MHz FSB.

http://images.dailytech.com/files/tulsa.png


RE: So many errors
By IntelUser2000 on 5/29/2006 2:43:52 AM , Rating: 4
For a article that claims Itanium 2 has shared L3, its a big claim. Did you get that directly from Intel?? Link: http://www.theinquirer.net/?article=31990

Inquirer disagrees with you.

Anandtech used to be source of reliable information, but its losing a lot of that lately.


RE: So many errors
By PT2006 on 5/29/2006 3:36:29 AM , Rating: 2
It might be difficult to grasp, but the inquirer gets it wrong... a lot... often.

I'm guessing you work there.


RE: So many errors
By KristopherKubicki (blog) on 5/29/2006 3:55:25 AM , Rating: 2
quote:
For a article that claims Itanium 2 has shared L3

We wrote that it was in the lineup. Shared L3 cache has been in Intel's since Montecito was first announced but probably will not show up until Montvale.

quote:
Anandtech used to be source of reliable information, but its losing a lot of that lately.

DailyTech and AnandTech are separate entities.


RE: So many errors
By Sunbird on 5/29/2006 7:02:35 AM , Rating: 2
Well, they are hosted on the same servers. When either site is down the other is down. They should physically seperate, then both arent dead at the same time, and I can still read the one that isn't down.

And another thing, I had to go back to the posted comments 4 times before I got my reply to be behind the correct message, the 3 times before it wanted to put my reply behind other messages although I had definitely clicked reply for the message I had wanted to reply too. Someone look into this please.


RE: So many errors
By KristopherKubicki (blog) on 5/29/2006 11:33:29 AM , Rating: 2
AnandTech, DailyTech, Xbit Labs and PCPerspective all use the same NOC.


Moderated
By KristopherKubicki (blog) on 5/28/06, Rating: -1
L III cache
By Borinquencmptrs on 5/28/2006 8:34:32 PM , Rating: 2
Although, this may be the first time a cpu has used onboard level III cache, I do remember the K6III using external level III cache. This did speed up the chip quite well. I wonder when both AMD and Intel insert the onboard cache how much it will actually help...




RE: L III cache
By The Cheeba on 5/28/2006 9:15:06 PM , Rating: 2
Processors have used L3 for a while. A lot of Xeon MP, Itanium and Pentium EE processors used it. This is the first time I think anyone has used it in an x86 processor in a shared configuration (meaning both cores use the same cache pool).


RE: L III cache
By Griswold on 5/29/2006 4:45:41 AM , Rating: 2
Oh could you please show me which Pentium EE and Xeon has L3 cache?


RE: L III cache
By MrKaz on 5/29/2006 6:45:18 AM , Rating: 2
http://www.intel.com/support/processors/pentium4/s...

Pentium 4 Processors Extreme Edition
3.20, and 3.40 GHz


RE: L III cache
By Griswold on 5/29/2006 8:04:08 AM , Rating: 2
Thanks for clearing the EE part up. It was a serious question after all. Which also makes me wanna give the finger to those moderating it down..


RE: L III cache
By TheLiberalTruth on 5/29/2006 6:50:06 AM , Rating: 4
quote:
Oh could you please show me which Pentium EE and Xeon has L3 cache?


How about the first Pentium 4 EE?

From Wikipedia:

"Gallatin (Extreme Edition)

In September 2003, at the Intel Developer Forum, the Pentium 4 Extreme Edition (P4EE) was announced, just over a week before the launch of Athlon 64, and Athlon 64 FX (AMD64 FX). The design was mostly identical to Pentium 4 (to the extent that it would run in the same motherboards), but differed by an added 2 MiB of Level 3 cache."
From this page: http://en.wikipedia.org/wiki/Pentium_4


Looks to be a bandaid...
By Viditor on 5/28/06, Rating: 0
RE: Looks to be a bandaid...
By Saist on 5/28/2006 9:44:03 PM , Rating: 4
I asked Intel about this during E3, what happened to CSI. I didn't get a straight answer, but this is what I gathered:

CSI is pushed back to 2009 at the earliest. Intel believes that their own point to point protocol technology is un-needed and that the FSB isn't finished yet. With Conroe dropping gigahertz levels back down to sub-3ghz, the front side bus problems experienced with 3ghz+ prescotts shouldn't be initial issues. Intel appearently believes that Conroe will win back enough marketshare and mindshare to stave off AMD and the need to move to a HyperTransport-like connection fro the processor. It was indicated that Conroe will buy enough time for Intel to do some more work with FSB technologies and hopefully remain competitive out until 2008 and 2009.

Now, as I'm not Sharikou, I wasn't about to try to nail Intel on FSB issues in their home turf. I don't know whether or not Conroe will buy Intel enough time to iron out CSI, or if Conroe will buy enough time to design and utilize another iteration of the FSB.

What I am going to presume though is that if that if the competition gets too heavy, I would bet on Intel joining Hypertransport before getting CSI out the door.


RE: Looks to be a bandaid...
By mjp1618 on 5/29/2006 1:36:46 PM , Rating: 2
http://www.theregister.co.uk/2006/05/06/tukwila_fo...

This article, dated 6th May 2006, claims that the Itanium Tukwila will have CSI, and that it will be out by 2008.

Now, Nehalem is also due in 2008, so will that also have CSI.

Again, this article says 2008 for CSI.


RE: Looks to be a bandaid...
By daschneider on 5/30/2006 10:39:40 AM , Rating: 3
I'm not sure I buy that dropping the processor frequency with Conroe is going to help very much. Conroe is dual core, which means to keep both cores feed you need to supply 2x the data and instruction stream of the single core processor. This traffic still has to pass over the same shared bus. Things are only going to get worse with the move to quad core. Intel really needs to address the processor interconnect issue if they want to stay in the game.


Few things . . .
By saratoga on 5/28/2006 10:33:52 PM , Rating: 4
quote:
However, this new approach also opens new doors for cache misses and collisions as its theoretically possible for both cores to write to the same bit without careful data management. Even in the event of a cache collision, Intel has a new technology ready to correct the errors. This technology already exists on Itantium 2, as Pellston. Intel has renamed this technology to CST, or Cache Safe Technology.


Two cores writing to the same memory location at the exact same time probably means your code isn't thread safe and is about to crash.

Anyway, neither of those problems are specific to a shared L3 cache, and Pellston doesn't address the problem you imply. According to MS's docs, its just an enchancement to the traditional ECC bit that allows cache to be disabled on the fly if its generating errors. That doesn't really have anything to do with cache collisions.




RE: Few things . . .
By KristopherKubicki (blog) on 5/28/2006 11:03:21 PM , Rating: 2
I cleaned that up, thanks.


RE: Few things . . .
By spwatkins on 6/2/2006 4:10:21 PM , Rating: 2
quote:
Two cores writing to the same memory location at the exact same time probably means your code isn't thread safe and is about to crash.


It is often the case that two processors are trying to write to the same memory location in order to implement a spin-lock which is used to synchronize things and make the code thread-safe.


8 socket systems
By hstewarth on 5/28/2006 8:35:02 PM , Rating: 1
This sounds new for Xeon based system, I thought the max was 4 sockets..





RE: 8 socket systems
By Viditor on 5/28/2006 8:45:43 PM , Rating: 2
quote:
This sounds new for Xeon based system, I thought the max was 4 sockets..

No...as a matter of fact, IBM's Xeon based systems can use as many as 64 CPUs...
It's only the Woodcrest line that's limited to 2 CPUs at the moment (until at least Q3 of next year).


RE: 8 socket systems
By hstewarth on 5/29/2006 11:05:28 AM , Rating: 2
I know that the Woodcrest are DP Processors - but I thought the Xeon MP line was only 4P. I knew that a lot more than that in days of Pentium Pro. It must be normal motherboard manufactor only processing 4 socket systems.

Thanks for clearing up the misinformation.


"You can bet that Sony built a long-term business plan about being successful in Japan and that business plan is crumbling." -- Peter Moore, 24 hours before his Microsoft resignation

Related Articles
Hell Freezes Over: Dell Goes AMD
May 18, 2006, 5:13 PM
Intel Socket 771 Unmasked
February 23, 2006, 12:00 AM













botimage
Copyright 2014 DailyTech LLC. - RSS Feed | Advertise | About Us | Ethics | FAQ | Terms, Conditions & Privacy Information | Kristopher Kubicki