 Intel's Tulsa die shot
NetBurst has one last trick, the first x86 processors with shared L3 cache
Despite all the anticipation over Intel's Core architecture and the market release of Core 2 Duo, Intel's presence in the enterprise servers (four and more sockets) with NetBurst continues strong -- although AMD is making some significant headway in this space.
According to Intel's roadmaps, the first wave of Xeon MP processors based on Intel's Tulsa core will be slated for Q4'06. DailyTech has the following information on the 7100 series of Tulsa Xeon MP processors. Tulsa is compatible with Socket 604, on Intel's Truland platform. Intel just announced its new LGA 771 socket, and it is not uncommon for Intel to produce multiple socket variants of processors during transition years.
|
Intel Server Processor Roadmap
|
Processor Brand |
Processor Number |
|
Clock Speed FSB |
L3 Cache |
Release Date
|
|
Xeon MP
|
7140M |
|
3.4GHz / 800MHz |
16MB |
Q4'06
|
|
Xeon MP
|
7140N |
|
3.33GHz / 667MHz |
16MB |
Q4'06 |
|
Xeon MP
|
7130M |
|
3.2GHz / 800MHz |
8MB |
Q4'06 |
|
Xeon MP
|
7130N |
|
3.16GHz / 667MHz |
8MB |
Q4'06 |
|
Xeon MP
|
7120M |
|
3.0GHz / 800MHz |
4MB |
Q4'06 |
|
Xeon MP
|
7120N |
|
3.0GHz / 667MHz |
4MB |
Q4'06 |
|
Xeon MP
|
7110M |
|
2.6GHz / 800MHz |
4MB |
Q4'06 |
|
Xeon MP
|
7110N |
|
2.5GHz / 667MHz |
4MB |
Q4'06 |
|
|
Xeon MP 7130 and 7140 will have a 150W power envelope, while
7110 and 7120 will use a 95W envelope.
The biggest feature of Tulsa
will be large L3 cache sizes which range up to 16MB. These Tulsa processors are designed to scale to
four and eight socket systems, and each Tulsa CPU contains two cores with
HyperThreading support. For those keeping track at home, an eight socket
Paxville system will show 32 logical CPUs.
Tulsa is the
last of Intel's Netburst lineup, but Netburst does have a few tricks not found
on Core yet. For starters, the massive amounts of L3 cache found in Tulsa cores are shared
between both cores. Each CPU has an independent L2 cache still. AMD
revealed earlier this year that K8L will also use the same ideology, with
independent L2 and shared L3 cache. Intel has had shared L3 cache on its
Itanium 2 server lineup for years, but this is the first time such a feature
has appeared on x86.
This new shared cache has several advantages -- each CPU core can use the L3
cache without sending a request back to the system I/O redundantly.
In order to manage errors in the cache, Intel has technology that already exists on Itantium 2, dubbed
Pellston. Intel has incorporated this onto Tulsa but renamed the technology to CST, or Cache Safe
Technology.
Intel's Woodcrest based Xeon processors expected to launch on June 26. These
Woodcrest processors do not have HyperThreading, unlike Tulsa. Dual-core Woodcrest processors
have high front side bus speeds, shared L2 caches and use the Intel Core
architecture. However, Intel has no plans to replace NetBurst for Xeon
servers that use more than two sockets -- at least through Q2'07.
In 2007, Intel will
introduce Clovertown, a server varient of Kentsfield, Intel's
next-generation quad-core processor. Current Xeon MP processors based on
Paxville will begin to be phased out by new Tulsa cores, but the change will happen
throughout most of 2007. Intel just launched its Dempsey Xeon processors with fairly lackluster response.
"Well, we didn't have anyone in line that got shot waiting for our system." -- Nintendo of America Vice President Perrin Kaplan
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