Xeon MP 7130 and 7140 will have a 150W power envelope, while
7110 and 7120 will use a 95W envelope.
The biggest feature of Tulsa
will be large L3 cache sizes which range up to 16MB. These Tulsa processors are designed to scale to
four and eight socket systems, and each Tulsa CPU contains two cores with
HyperThreading support. For those keeping track at home, an eight socket
Paxville system will show 32 logical CPUs.
Tulsa is the
last of Intel's Netburst lineup, but Netburst does have a few tricks not found
on Core yet. For starters, the massive amounts of L3 cache found in Tulsa cores are shared
between both cores. Each CPU has an independent L2 cache still. AMD
revealed earlier this year that K8L will also use the same ideology, with
independent L2 and shared L3 cache. Intel has had shared L3 cache on its
Itanium 2 server lineup for years, but this is the first time such a feature
has appeared on x86.
This new shared cache has several advantages -- each CPU core can use the L3
cache without sending a request back to the system I/O redundantly.
In order to manage errors in the cache, Intel has technology that already exists on Itantium 2, dubbed
Pellston. Intel has incorporated this onto Tulsa but renamed the technology to CST, or Cache Safe
Intel's Woodcrest based Xeon processors expected to launch on June 26. These
Woodcrest processors do not have HyperThreading, unlike Tulsa. Dual-core Woodcrest processors
have high front side bus speeds, shared L2 caches and use the Intel Core
architecture. However, Intel has no plans to replace NetBurst for Xeon
servers that use more than two sockets -- at least through Q2'07.
In 2007, Intel will
introduce Clovertown, a server varient of Kentsfield, Intel's
next-generation quad-core processor. Current Xeon MP processors based on
Paxville will begin to be phased out by new Tulsa cores, but the change will happen
throughout most of 2007. Intel just launched its Dempsey Xeon processors with fairly lackluster response.
quote: Xeon MP 7130 and 7140 will have a 150W power envelope, while 7110 and 7120 will use a 95W envelope.
quote: Intel has had shared L3 cache on its Itanium 2 server lineup for years, but this is the first time such a feature has appeared on x86.
quote: For a article that claims Itanium 2 has shared L3
quote: Anandtech used to be source of reliable information, but its losing a lot of that lately.
quote: Oh could you please show me which Pentium EE and Xeon has L3 cache?
quote: However, this new approach also opens new doors for cache misses and collisions as its theoretically possible for both cores to write to the same bit without careful data management. Even in the event of a cache collision, Intel has a new technology ready to correct the errors. This technology already exists on Itantium 2, as Pellston. Intel has renamed this technology to CST, or Cache Safe Technology.
quote: Two cores writing to the same memory location at the exact same time probably means your code isn't thread safe and is about to crash.
quote: This sounds new for Xeon based system, I thought the max was 4 sockets..